Timing Channels in Cryptography (Record no. 51563)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03298nam a22005055i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-319-12370-7 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200420220215.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 141212s2015 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783319123707 |
| -- | 978-3-319-12370-7 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.382 |
| 100 1# - AUTHOR NAME | |
| Author | Rebeiro, Chester. |
| 245 10 - TITLE STATEMENT | |
| Title | Timing Channels in Cryptography |
| Sub Title | A Micro-Architectural Perspective / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XVII, 152 p. 75 illus., 14 illus. in color. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | An Introduction to Timing Attacks -- Modern Cryptography -- Superscalar Processors, Cache Memories, and Branch Predictors -- Time-Driven Cache Attacks -- Advanced Time-Driven Cache Attacks on Block Ciphers -- A Formal Analysis of Time-Driven Cache Attacks -- Profiled Time-Driven Cache Attacks on Block Ciphers -- Access-Driven Cache Attacks on Block Ciphers -- Branch Prediction Attacks -- Countermeasures for Timing Attacks. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book deals with timing attacks on software implementations of encryption algorithms. It describes and analyzes various unintended covert timing channels that are formed when ciphers are executed in microprocessors. Modern superscalar microprocessors are considered, which are enabled with features such as multi-threaded, pipelined, parallel, speculative, and out-of-order execution. Various timing attack algorithms are described and analyzed for block ciphers as well as public-key ciphers. The interplay between the cipher implementation, system architecture, and the attack's success is analyzed. Further hardware and software countermeasures are discussed with the aim of illustrating methods to build systems that can protect against these attacks. Discusses various timing attack algorithms in detail allowing readers to reconstruct the attack. Provides several experimental results to support the theoretical analysis provided in the book. Analyzes information leakage from cache memories and branch prediction units in the processor. Examines information leakage models that would help quantify leakage in a covert timing channels. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Mukhopadhyay, Debdeep. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Bhattacharya, Sarani. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-3-319-12370-7 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2015. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Data structures (Computer science). |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Signal, Image and Speech Processing. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Data Structures, Cryptology and Information Theory. |
| 912 ## - | |
| -- | ZDB-2-ENG |
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