SystemVerilog Assertions and Functional Coverage (Record no. 52175)

000 -LEADER
fixed length control field 03797nam a22004815i 4500
001 - CONTROL NUMBER
control field 978-1-4614-7324-4
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20200420220225.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 130805s2014 xxu| s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9781461473244
-- 978-1-4614-7324-4
082 04 - CLASSIFICATION NUMBER
Call Number 621.3815
100 1# - AUTHOR NAME
Author Mehta, Ashok B.
245 10 - TITLE STATEMENT
Title SystemVerilog Assertions and Functional Coverage
Sub Title Guide to Language, Methodology and Applications /
300 ## - PHYSICAL DESCRIPTION
Number of Pages XXXIII, 356 p.
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions - Basics (sequence, property, assert).- Sampled Value Functions   $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- 'expect' -- 'assume' and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800-2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions - LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options (Reference material).
520 ## - SUMMARY, ETC.
Summary, etc This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage.  Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'.  Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.  Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby reducing drastically their time to design and debug.   �         Covers both SystemVerilog Assertions and SytemVerilog Functional Coverage language and methodologies; �         Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; �         Explains each concept in an easy to understand, step-by-step fashion and applies it to a real example; �         Includes practical labs that enable readers to put in practice the concepts explained in the book.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/978-1-4614-7324-4
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
264 #1 -
-- New York, NY :
-- Springer New York :
-- Imprint: Springer,
-- 2014.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
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-- online resource
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-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Engineering.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Microprocessors.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronics.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Microelectronics.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuits.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Engineering.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronics and Microelectronics, Instrumentation.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Processor Architectures.
912 ## -
-- ZDB-2-ENG

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