High-Performance Computing Using FPGAs (Record no. 54002)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04853nam a22004935i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-1-4614-1791-0 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200421111204.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 130502s2013 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781461417910 |
| -- | 978-1-4614-1791-0 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 245 10 - TITLE STATEMENT | |
| Title | High-Performance Computing Using FPGAs |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XI, 803 p. 232 illus. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | High-Performance Hardware Acceleration of Asset Simulations -- Monte Carlo Simulation based Financial Computing on the Maxwell FPGA Parallel Machine -- Bioinformatics Applications on the FPGA-based High-Performance Computer RIVYERA -- FPGA-Accelerated Molecular Dynamics -- FPGA-based HPRC for Bioinformatics Applications -- High-Performance Computing for Neuroinformatics using FPGA -- High-Performance FPGA-Accelerated Real-time Search -- High-Performance Data Processing over N-ary Trees -- FPGA-based Systolic Computational-Memory Array for Scalable Stencil Computations -- High performance implementation of RTM seismic modeling on FPGAs: architecture, arithmetic and power issues -- High-Performance Cryptanalysis on RIVYERA and COPACOBANA Computing Systems -- FPGA-based HPRC Systems for Scientific Applications -- Accelerating the SPICE Circuit Simulator using an FPGA - A Case Study -- The Convey Hybrid-Core Architecture -- Low Cost High Performance Reconfigurable Computing -- An FPGA-based supercomputer for statistical physics: the weird case of Janus -- Accelerate Communication, not Computation! -- High-speed torus interconnect using FPGAs -- MEMSCALE: Re-architecting memory resources for clusters -- High-performance computing based on high-speed dynamic reconfiguration -- Reconfigurable arithmetic for HPC -- Acceleration of the Discrete Element Method: From RTL to C-Based Design -- Optimising Euroben Kernels on Maxwell -- Assessing Productivity of High-Level Design Methodologies for High-Performance Reconfigurable Computers -- Maximum performance computing with dataflow engines. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book is concerned with the emerging field of High Performance Reconfigurable Computing (HPRC), which aims to harness the high performance and relative low power of reconfigurable hardware-in the form Field Programmable Gate Arrays (FPGAs)-in High Performance Computing (HPC) applications. It presents the latest developments in this field from applications, architecture, and tools and methodologies points of view. We hope that this work will form a reference for existing researchers in the field, and entice new researchers and developers to join the HPRC community. The book includes: Thirteen application chapters which present the most important application areas tackled by high performance reconfigurable computers, namely: financial computing, bioinformatics and computational biology, data search and processing, stencil computation e.g. computational fluid dynamics and seismic modeling, cryptanalysis, astronomical N-body simulation, and circuit simulation. Seven architecture chapters which present both commercial and academic parallel FPGA architectures, low latency and high performance FPGA-based networks and memory architectures for parallel machines, and a high speed optical dynamic reconfiguration mechanism for HPRC. Five tools and methodologies chapters which address the important issue of productivity and high performance in HPRC. These include a study of precision and arithmetic issues in HPRC, comparative studies of C-based high level synthesis tools and RTL-based approaches, taxonomy of HPRC tools and a framework of their analysis, and an integrated hardware-software-application approach to HPRC. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Vanderbauwhede, Wim. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Benkrid, Khaled. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-1-4614-1791-0 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | New York, NY : |
| -- | Springer New York : |
| -- | Imprint: Springer, |
| -- | 2013. |
| 336 ## - | |
| -- | text |
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| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Information theory. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Information and Communication, Circuits. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Devices. |
| 912 ## - | |
| -- | ZDB-2-ENG |
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