Finite State Machine Logic Synthesis for Complex Programmable Logic Devices (Record no. 57248)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 02719nam a22005055i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-642-36166-1 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200421112052.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 130125s2013 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783642361661 |
| -- | 978-3-642-36166-1 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Czerwinski, Robert. |
| 245 10 - TITLE STATEMENT | |
| Title | Finite State Machine Logic Synthesis for Complex Programmable Logic Devices |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XV, 172 p. |
| 490 1# - SERIES STATEMENT | |
| Series statement | Lecture Notes in Electrical Engineering, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Introduction -- Definitions and Basic Properties -- Synthesis of FSMs -- State Assignment Algorithms -- Theoretical Background of Technology-Dependent Optimization -- The Algorithm of Area Optimization Based on Graphs of Outputs -- Conclusions -- Output File Format -- Conclusion. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can also be interpreted as programmable AND-fixed OR structure, well known as PAL-based structure. The question is: what should be done when the number of implicants representing function exceeds the number of product terms available in a logic block. The answer is ... in the book. Logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Kania, Dariusz. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-3-642-36166-1 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Berlin, Heidelberg : |
| -- | Springer Berlin Heidelberg : |
| -- | Imprint: Springer, |
| -- | 2013. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering design. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logic Design. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering Design. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 1876-1100 ; |
| 912 ## - | |
| -- | ZDB-2-ENG |
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