Design, Analysis and Test of Logic Circuits Under Uncertainty (Record no. 57266)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 03642nam a22005895i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-90-481-9644-9 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200421112052.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 120921s2013 ne | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9789048196449 |
| -- | 978-90-481-9644-9 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Krishnaswamy, Smita. |
| 245 10 - TITLE STATEMENT | |
| Title | Design, Analysis and Test of Logic Circuits Under Uncertainty |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XII, 124 p. |
| 490 1# - SERIES STATEMENT | |
| Series statement | Lecture Notes in Electrical Engineering, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Introduction -- Probabilistic Transfer Matrices -- Computing with Probabilistic Transfer Matrices -- Testing Logic Circuits for Probabilistic Faults -- Signtaure-based Reliability Analysis -- Design for Robustness -- Summary and Extensions. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits. To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits. The book describes techniques for: • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework; • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-level optimizations; • Logic synthesis for greater resilience against soft errors, which improves reliability using moderate overhead in area and performance; • Test-generation and test-compaction methods aimed at probabilistic faults in logic circuits that facilitate accurate and efficient post-manufacture measurement of soft-error susceptibility. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Reusability. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Mathematics. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Markov, Igor L. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Hayes, John P. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-90-481-9644-9 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Dordrecht : |
| -- | Springer Netherlands : |
| -- | Imprint: Springer, |
| -- | 2013. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer hardware. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Arithmetic and logic units, Computer. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer software |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer science |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Arithmetic and Logic Structures. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer Hardware. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Performance and Reliability. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logic Design. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Symbolic and Algebraic Manipulation. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 1876-1100 ; |
| 912 ## - | |
| -- | ZDB-2-ENG |
No items available.