Central Library

RTL hardware design using VHDL : (Record no. 59358)

000 -LEADER
fixed length control field 06195nam a2201177 i 4500
001 - CONTROL NUMBER
control field 5237648
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20200421114111.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 151221s2006 njua ob 001 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9780471786412
-- ebook
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9786610448104
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
-- print
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
-- alk. paper
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
-- electronic
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
-- electronic
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
-- electronic
082 04 - CLASSIFICATION NUMBER
Call Number 621.39/2
100 1# - AUTHOR NAME
Author Chu, Pong P.,
245 10 - TITLE STATEMENT
Title RTL hardware design using VHDL :
Sub Title coding for efficiency, portability, and scalability /
300 ## - PHYSICAL DESCRIPTION
Number of Pages 1 PDF (xxiii, 669 pages) :
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Introduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice.
520 ## - SUMMARY, ETC.
Summary, etc The skills and guidance needed to master RTL hardware design This book teaches readers how to systematically design efficient, portable, and scalable Register Transfer Level (RTL) digital circuits using the VHDL hardware description language and synthesis software. Focusing on the module-level design, which is composed of functional units, routing circuit, and storage, the book illustrates the relationship between the VHDL constructs and the underlying hardware components, and shows how to develop codes that faithfully reflect the module-level design and can be synthesized into efficient gate-level implementation. Several unique features distinguish the book: * Coding style that shows a clear relationship between VHDL constructs and hardware components * Conceptual diagrams that illustrate the realization of VHDL codes * Emphasis on the code reuse * Practical examples that demonstrate and reinforce design concepts, procedures, and techniques * Two chapters on realizing sequential algorithms in hardware * Two chapters on scalable and parameterized designs and coding * One chapter covering the synchronization and interface between multiple clock domains Although the focus of the book is RTL synthesis, it also examines the synthesis task from the perspective of the overall development process. Readers learn good design practices and guidelines to ensure that an RTL design can accommodate future simulation, verification, and testing needs, and can be easily incorporated into a larger system or reused. Discussion is independent of technology and can be applied to both ASIC and FPGA devices. With a balanced presentation of fundamentals and practical examples, this is an excellent textbook for upper-level undergraduate or graduate courses in advanced digital logic. Engineers who need to make effective use of today's synthesis software and FPGA devices should also refer to this book.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
General subdivision Data processing.
856 42 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5237648
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
264 #1 -
-- Hoboken, New Jersey :
-- Wiley-Interscience,
-- c2006.
264 #2 -
-- [Piscataqay, New Jersey] :
-- IEEE Xplore,
-- [2006]
336 ## -
-- text
-- rdacontent
337 ## -
-- electronic
-- isbdmedia
338 ## -
-- online resource
-- rdacarrier
588 ## -
-- Description based on PDF viewed 12/21/2015.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Digital electronics
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- VHDL (Computer hardware description language)
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-- Adders
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-- Aggregates
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-- Algorithm design and analysis
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-- Application specific integrated circuits
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-- Arrays
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-- Bibliographies
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-- Books
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-- Clocks
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-- Complexity theory
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-- Computational modeling
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-- Computer architecture
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-- Decoding
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-- Delay
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-- Design methodology
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-- Digital systems
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-- Encoding
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-- Field programmable gate arrays
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-- Finite element methods
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-- Generators
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-- Hardware
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-- Hardware design languages
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-- Heuristic algorithms
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-- IEEE standards
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-- Indexes
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-- Integrated circuit interconnections
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-- Integrated circuit modeling
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-- Latches
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-- Libraries
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-- Logic gates
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-- Memory management
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-- Multiplexing
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-- Organizations
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-- Process control
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-- Pulse generation
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-- Radiation detectors
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-- Random access memory
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-- Receivers
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-- Registers
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-- Routing
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-- Sections
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-- Semantics
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-- Sensitivity
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-- Sequential circuits
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-- Skeleton
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-- Software
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-- Software algorithms
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-- Synchronization
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-- Syntactics
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-- Time factors
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-- Timing
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-- Transistors

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