Routing in the third dimension : (Record no. 73874)
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000 -LEADER | |
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fixed length control field | 03956nam a2200949 i 4500 |
001 - CONTROL NUMBER | |
control field | 5263943 |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20220712205642.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 151221s1995 njua ob 001 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 9780470546376 |
-- | electronic |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
-- | |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
-- | electronic |
082 04 - CLASSIFICATION NUMBER | |
Call Number | 621.39/5 |
100 1# - AUTHOR NAME | |
Author | Sherwani, N. A., |
245 10 - TITLE STATEMENT | |
Title | Routing in the third dimension : |
Sub Title | from VLSI chips to MCMs / |
300 ## - PHYSICAL DESCRIPTION | |
Number of Pages | 1 PDF (xviii, 358 pages) : |
505 0# - FORMATTED CONTENTS NOTE | |
Remark 2 | Preface. Acknowledgments. Introduction. Graphs and Basic Algorithms. Channel Routing and Terminal Assignment. Routing Models. Basic Problems in Routing. Routing Algorithms for the Two-Layer Process. Routing Algorithms for the Three-Layer Process. Routing Algorithms for the Advanced Three-Layered Process. Routing Algorithms for Advanced VLSI and Thin-Film MCMs. Routing Algorithms for General MCMs. Bibliography. Author Index. Subject Index. |
520 ## - SUMMARY, ETC. | |
Summary, etc | This key text addresses the complex computer chips of tomorrow which will consist of several layers of metal interconnect, making the interconnect within a chip or a multichip module a three dimensional problem. You'll find an insightful approach to the algorithmic, cell design issues in chip and MCM routing with an emphasis on techniques for eliminating routing area. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
Subject | Integrated circuits |
General subdivision | Very large scale integration |
-- | Computer-aided design. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
Subject | Multichip modules (Microelectronics) |
General subdivision | Computer-aided design. |
700 1# - AUTHOR 2 | |
Author 2 | Bhingarde, Siddharth. |
700 1# - AUTHOR 2 | |
Author 2 | Panyam, Anand. |
856 42 - ELECTRONIC LOCATION AND ACCESS | |
Uniform Resource Identifier | https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5263943 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | eBooks |
264 #1 - | |
-- | Piscataway, New Jersey : |
-- | IEEE Press, |
-- | c1995. |
264 #2 - | |
-- | [Piscataqay, New Jersey] : |
-- | IEEE Xplore, |
-- | [1995] |
336 ## - | |
-- | text |
-- | rdacontent |
337 ## - | |
-- | electronic |
-- | isbdmedia |
338 ## - | |
-- | online resource |
-- | rdacarrier |
588 ## - | |
-- | Description based on PDF viewed 12/21/2015. |
695 ## - | |
-- | Algorithm design and analysis |
695 ## - | |
-- | Approximation algorithms |
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-- | Approximation methods |
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-- | Bibliographies |
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-- | Bipartite graph |
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-- | CMOS integrated circuits |
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-- | Classification algorithms |
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-- | Color |
695 ## - | |
-- | Compaction |
695 ## - | |
-- | Complexity theory |
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-- | Computer architecture |
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-- | Delay |
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-- | Estimation |
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-- | Fabrication |
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-- | Heuristic algorithms |
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-- | Indexes |
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-- | Integrated circuit interconnections |
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-- | Integrated circuit modeling |
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-- | Layout |
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-- | Libraries |
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-- | Logic gates |
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-- | Mathematical model |
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-- | Metals |
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-- | Microprocessors |
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-- | Minimization |
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-- | Nickel |
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-- | Pins |
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-- | Polynomials |
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-- | Regions |
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-- | Routing |
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-- | Shape |
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-- | Substrates |
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-- | Terminology |
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-- | Transistors |
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-- | Very large scale integration |
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-- | Wire |
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