Low-Power Design and Power-Aware Verification (Record no. 79419)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03546nam a22005535i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-319-66619-8 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220801221219.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 171005s2018 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783319666198 |
| -- | 978-3-319-66619-8 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Khondkar, Progyna. |
| 245 10 - TITLE STATEMENT | |
| Title | Low-Power Design and Power-Aware Verification |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2018. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XV, 155 p. 19 illus., 12 illus. in color. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | 1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References. . |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers. . |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-3-319-66619-8 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2018. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Software engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer architecture. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computers. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Software Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Hardware Performance and Reliability. |
| 912 ## - | |
| -- | ZDB-2-ENG |
| 912 ## - | |
| -- | ZDB-2-SXE |
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