Digital System Verification (Record no. 85378)

000 -LEADER
fixed length control field 04156nam a22005655i 4500
001 - CONTROL NUMBER
control field 978-3-031-79815-3
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20240730164157.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 220601s2010 sz | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783031798153
-- 978-3-031-79815-3
082 04 - CLASSIFICATION NUMBER
Call Number 620
100 1# - AUTHOR NAME
Author Li, Lun.
245 10 - TITLE STATEMENT
Title Digital System Verification
Sub Title A Combined Formal Methods and Simulation Framework /
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2010.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XIV, 79 p.
490 1# - SERIES STATEMENT
Series statement Synthesis Lectures on Digital Circuits & Systems,
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Introduction -- Formal Methods Background -- Simulation Approaches -- Integrated Design Validation System -- Conclusion and Summary.
520 ## - SUMMARY, ETC.
Summary, etc Integrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design with respect to its specification through mathematical proof techniques. Formal techniques have been emerging as commercialized EDA tools in the past decade. Simulation remains a predominantly used tool to validate a design in industry. After more than 50 years of development, simulation methods have reached a degree of maturity, however, new advances continue to be developed in the area. A simulation approach for functional verification can theoretically validate all possible behaviors of a design but requires excessive computational resources. Rapidly evolving markets demand short design cycles while the increasing complexity of a design causes simulation approaches to provide less and less coverage. Formal verification is an attractive alternative since 100% coverage can be achieved; however, large designs impose unrealistic computational requirements. Combining formal verification and simulation into a single integrated circuit validation framework is an attractive alternative. This book focuses on an Integrated Design Validation (IDV) system that provides a framework for design validation and takes advantage of current technology in the areas of simulation and formal verification resulting in a practical validation engine with reasonable runtime. After surveying the basic principles of formal verification and simulation, this book describes the IDV approach to integrated circuit functional validation. Table of Contents: Introduction / Formal Methods Background / Simulation Approaches / Integrated Design Validation System/ Conclusion and Summary.
700 1# - AUTHOR 2
Author 2 Thornton, Mitchel.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier https://doi.org/10.1007/978-3-031-79815-3
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
264 #1 -
-- Cham :
-- Springer International Publishing :
-- Imprint: Springer,
-- 2010.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Engineering.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuits.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Control engineering.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Robotics.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Automation.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computers.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Technology and Engineering.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Control, Robotics, Automation.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computer Hardware.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
-- 1932-3174
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-- ZDB-2-SXSC

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