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Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation (Record no. 97198)

000 -LEADER
fixed length control field 06994nam a22006495i 4500
001 - CONTROL NUMBER
control field 978-3-642-11802-9
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20240730202826.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 100305s2010 gw | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9783642118029
-- 978-3-642-11802-9
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-3-642-11802-9
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA76.9.S88
072 #7 - SUBJECT CATEGORY CODE
Subject category code UYD
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code COM011000
Source bisacsh
072 #7 - SUBJECT CATEGORY CODE
Subject category code UYD
Source thema
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 004.2
Edition number 23
245 10 - TITLE STATEMENT
Title Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation
Medium [electronic resource] :
Remainder of title 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers /
Statement of responsibility, etc. edited by José Monteiro, Rene van Leuken.
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2010.
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture Berlin, Heidelberg :
Name of producer, publisher, distributor, manufacturer Springer Berlin Heidelberg :
-- Imprint: Springer,
Date of production, publication, distribution, manufacture, or copyright notice 2010.
300 ## - PHYSICAL DESCRIPTION
Extent 370 p. 234 illus.
Other physical details online resource.
336 ## - CONTENT TYPE
Content type term text
Content type code txt
Source rdacontent
337 ## - MEDIA TYPE
Media type term computer
Media type code c
Source rdamedia
338 ## - CARRIER TYPE
Carrier type term online resource
Carrier type code cr
Source rdacarrier
347 ## - DIGITAL FILE CHARACTERISTICS
File type text file
Encoding format PDF
Source rda
490 1# - SERIES STATEMENT
Series statement Theoretical Computer Science and General Issues,
International Standard Serial Number 2512-2029 ;
Volume/sequential designation 5953
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Keynotes -- Robust Low Power Embedded SRAM Design: From System to Memory Cell -- Variability in Advanced Nanometer Technologies: Challenges and Solutions -- Subthreshold Circuit Design for Ultra-Low-Power Applications -- Special Session -- SystemC AMS Extensions: New Language - New Methods - New Applications -- Session 1: Variability & Statistical Timing -- Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation -- Interpreting SSTA Results with Correlation -- Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units -- Exponent Monte Carlo for Quick Statistical Circuit Simulation -- Poster Session 1: Circuit Level Techniques -- Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis -- A Hardware Implementation of the User-Centric Display Energy Management -- On-chip Thermal Modeling Based on SPICE Simulation -- Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures -- Session 2: Power Management -- Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip -- Data-Driven Clock Gating for Digital Filters -- Power Management and Its Impact on Power Supply Noise -- Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems -- Session 3: Low Power Circuits & Technology -- Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique -- Crosstalk in High-Performance Asynchronous Designs -- Modeling and Reducing EMI in GALS and Synchronous Systems -- Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop -- Poster Session 2: System Level Techniques -- Multi-granularity NoC Simulation Framework for Early PhaseExploration of SDR Hardware Platforms -- Dynamic Data Type Optimization and Memory Assignment Methodologies -- Accelerating Embedded Software Power Profiling Using Run-Time Power Emulation -- Write Invalidation Analysis in Chip Multiprocessors -- Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform -- BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation -- Session 4: Power & Timing Optimization Techniques -- Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering -- Low Energy Voltage Dithering in Dual V DD Circuits -- Product On-Chip Process Compensation for Low Power and Yield Enhancement -- Session 5: Self-timed Circuits -- Low-Power Soft Error Hardened Latch -- Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities -- Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation -- The Magic Rule of Tiles: Virtual Delay Insensitivity -- Session 6: Low Power Circuit Analysis & Optimization -- Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates -- A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR) -- Routing Resistance Influence in Loading Effect on Leakage Analysis -- Session 7: Low Power Design Studies -- Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor Networks -- An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process -- Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V t Domain By Architectural Folding -- A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder.
520 ## - SUMMARY, ETC.
Summary, etc. This book constitutes the thoroughly refereed post-conference proceedings of 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, featuring Integrated Circuit and System Design, held in Delft, The Netherlands during September 9-11, 2009. The 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies. .
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer systems.
9 (RLIN) 173234
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer programming.
9 (RLIN) 4169
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer engineering.
9 (RLIN) 10164
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer networks .
9 (RLIN) 31572
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Microprocessors.
9 (RLIN) 173235
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer architecture.
9 (RLIN) 3513
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer simulation.
9 (RLIN) 5106
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computers.
9 (RLIN) 8172
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer System Implementation.
9 (RLIN) 38514
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Programming Techniques.
9 (RLIN) 173236
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer Engineering and Networks.
9 (RLIN) 173237
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Processor Architectures.
9 (RLIN) 173238
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer Modelling.
9 (RLIN) 173239
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer Hardware.
9 (RLIN) 33420
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Monteiro, José.
Relator term editor.
Relationship edt
-- http://id.loc.gov/vocabulary/relators/edt
9 (RLIN) 173240
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name van Leuken, Rene.
Relator term editor.
Relationship edt
-- http://id.loc.gov/vocabulary/relators/edt
9 (RLIN) 173241
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
9 (RLIN) 173242
773 0# - HOST ITEM ENTRY
Title Springer Nature eBook
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Printed edition:
International Standard Book Number 9783642118012
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Printed edition:
International Standard Book Number 9783642118036
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Theoretical Computer Science and General Issues,
International Standard Serial Number 2512-2029 ;
Volume/sequential designation 5953
9 (RLIN) 173243
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="https://doi.org/10.1007/978-3-642-11802-9">https://doi.org/10.1007/978-3-642-11802-9</a>
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-- ZDB-2-SXCS
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-- ZDB-2-LNC
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks-Lecture Notes in CS

No items available.