Normal view MARC view ISBD view

Digital VLSI Design with Verilog [electronic resource] : A Textbook from Silicon Valley Polytechnic Institute / by John Michael Williams.

By: Williams, John Michael [author.].
Contributor(s): SpringerLink (Online service).
Material type: materialTypeLabelBookPublisher: Cham : Springer International Publishing : Imprint: Springer, 2014Edition: 2nd ed. 2014.Description: XVI, 553 p. 273 illus., 116 illus. in color. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783319047898.Subject(s): Engineering | Microprocessors | Electronics | Microelectronics | Electronic circuits | Engineering | Circuits and Systems | Processor Architectures | Electronics and Microelectronics, InstrumentationAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Introductory Material -- Week 1 Class 1 -- Week 1 Class 2 -- Week 2 Class 1 -- Week 2 Class 2 -- Week 3 Class 1 -- Week 3 Class 2 -- Week 4 Class 1 -- Week 4 Class 2 -- Week 5 Class 1 -- Week 5 Class 2 -- Week 6 Class 1 -- Week 6 Class 2 -- Week 7 Class 1 -- Week 7 Class 2 -- Week 8 Class 1 -- Week 8 Class 2 -- Week 9 Class 1 -- Week 9 Class 2 -- Week 10 Class 1 -- Week 10 Class 2 -- Week 11 Class 1 -- Week 11 Class 2 -- Week 12 Class 1 -- Week 12 Class 2.
In: Springer eBooksSummary: This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics includes SystemVerilog and Verilog-AMS.   Covers the entire Verilog language - using most of it in practice; Provides 27 lab exercises, with complete and tested answers; Explains and emphasizes synthesizability, wherever it pertains to language features; Develops as a major project a synthesizable 70,000-gate SerDes; Presents synthesis-relevant usage of SystemVerilog, and the basic functionality of Verilog-AMS. >.
    average rating: 0.0 (0 votes)
No physical items for this record

Introductory Material -- Week 1 Class 1 -- Week 1 Class 2 -- Week 2 Class 1 -- Week 2 Class 2 -- Week 3 Class 1 -- Week 3 Class 2 -- Week 4 Class 1 -- Week 4 Class 2 -- Week 5 Class 1 -- Week 5 Class 2 -- Week 6 Class 1 -- Week 6 Class 2 -- Week 7 Class 1 -- Week 7 Class 2 -- Week 8 Class 1 -- Week 8 Class 2 -- Week 9 Class 1 -- Week 9 Class 2 -- Week 10 Class 1 -- Week 10 Class 2 -- Week 11 Class 1 -- Week 11 Class 2 -- Week 12 Class 1 -- Week 12 Class 2.

This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics includes SystemVerilog and Verilog-AMS.   Covers the entire Verilog language - using most of it in practice; Provides 27 lab exercises, with complete and tested answers; Explains and emphasizes synthesizability, wherever it pertains to language features; Develops as a major project a synthesizable 70,000-gate SerDes; Presents synthesis-relevant usage of SystemVerilog, and the basic functionality of Verilog-AMS. >.

There are no comments for this item.

Log in to your account to post a comment.