Description based upon print version of record.

1.3. Heuristics and metaheuristics -- 1.3.1. Definitions -- 1.3.2. Graph theory -- 1.3.3. Branch and bound technique -- 1.3.4. Tabu search technique -- 1.3.5. Simulated annealing technique -- 1.3.6. Genetic and evolutionary algorithms -- 1.4. Conclusion -- 2. Basic Notions on the Design of Digital Circuits and Systems -- 2.1. Introduction -- 2.2. History of VLSI circuit design -- 2.2.1. Prediffused circuit -- 2.2.2. Sea of gates -- 2.2.3. Field-programmable gate array -- FPGA -- 2.2.4. Elementary pre-characterized circuit (standard cells) -- 2.2.5. Full-custom circuit -- 2.2.6. Silicon compilation

2.3. System design level -- 2.3.1. Synthesis -- 2.3.2. Floorplanning -- 2.3.3. Analysis -- 2.3.4. Verification -- 2.4. Register transfer design level -- 2.4.1. Synthesis -- 2.4.2. Analysis -- 2.4.3. Verification -- 2.5. Module design level -- 2.5.1. Synthesis -- 2.5.2. Analysis -- 2.5.3. Verification -- 2.6. Gate design level -- 2.6.1. Synthesis -- 2.6.2. Analysis -- 2.6.3. Verification -- 2.7. Transistor level -- 2.7.1. NMOS and CMOS technologies -- 2.7.2. Theory of MOS transistor (current IDS) -- 2.7.3. Transfer characteristics of the inverter -- 2.7.4. Static analysis of the inverter

2.7.5. Threshold voltage of the inverter -- 2.7.6. Estimation of the rise and fall times of a capacitor -- 2.8. Interconnections -- 2.8.1. Synthesis of interconnections -- 2.8.2. Synthesis of networks-on-chip -- 2.9. Conclusion -- 3.Case Study: Application of Heuristics and Metaheuristics in the Design of Integrated Circuits and Systems -- 3.1. Introduction -- 3.2. System level -- 3.2.1. Synthesis of systems-on-chip (SoCs) with low energy consumption -- 3.2.2. Heuristic application to dynamic voltage and frequency scaling (DVFS) for the design of a real-time system subject to energy constraint

3.3. Register transfer level -- 3.3.1. Integer linear programming applied to the scheduling of operations of a data flow graph (DFG) -- 3.3.2. The scheduling of operations in a controlled data flow graph (considering the speed-power consumption tradeoff) -- 3.3.3. Efficient code assignment to the states of a finite state machine (aimed at reaching an effective control part in terms of surface, speed and power consumption)

3.3.4. Synthesis of submicron transistors and interconnections for the design of high-performance (low-power) circuits subject to power (respectively time) and surface constraints

Includes bibliographical references and index.

John Wiley and Sons Wiley Frontlist Obook All English 2020