Integrated circuit manufacturability : the art of process and design integration / edited by Jos�e Pineda de Gyvez, Dhiraj Pradhan.
Contributor(s): Pradhan, Dhiraj K
| Pineda de Gyvez, Jos�e | John Wiley & Sons [publisher.] | IEEE Circuits and Systems Society | IEEE Xplore (Online service) [distributor.].
Material type: 
BookPublisher: Piscataway, New Jersey : IEEE Press, c1999Distributor: [Piscataqay, New Jersey] : IEEE Xplore, [1998]Description: 1 PDF (xv, 316 pages) : illustrations.Content type: text Media type: electronic Carrier type: online resourceISBN: 9780470544921.Subject(s): Integrated circuits -- Computer-aided design | Metal oxide semiconductors, Complementary -- Computer-aided design | Integrated circuits -- Testing | Delay | Digital signal processing | Fault tolerance | Fault tolerant systems | Indexes | Integrated circuit modeling | Integrated circuits | Layout | Lithography | Logic gates | Maintenance engineering | Manufacturing | Manufacturing processes | Materials | Mathematical model | Metals | Mobile communication | Monitoring | Probes | Production | RLC circuits | Random variables | Reliability | Sections | Semiconductor device modeling | Solid modeling | Statistical analysis | Substrates | Testing | Very large scale integration | Assembly | Atmospheric modeling | Biographies | CMOS integrated circuits | Circuit faults | Circuit optimization | Circuit synthesis | Computational modeling | ContaminationGenre/Form: Electronic books.Additional physical formats: Print version:: No titleDDC classification: 621.3815 Online resources: Abstract with links to resource Also available in print."IEEE Circuits and Systems Society, sponsor."
Includes bibliographical references and index.
Preface. Introduction (Jose Pineda de Gyvez). Defect Monitoring and Characterization (Eric Bruls). Digital CMOS Fault Modeling and Inductive Fault Analysis (Manoj Sachdev). Functional Yield Modeling (Gary C. Cheek and Geoff O'Donoghue). Critical Area and Fault Probability Prediction (D.M.H. Walker). Statistical Methods of Parametric Yield and Quality Enhancement (Maciej Styblinski). Architectural Fault Tolerance (S.K. Tewksbury). Design for Test and Manufacturability (Dhiraj Pradhan and Adit Singh). Testing Solutions for MCM Manufacturing (Yervant Zorian). Index. About the Editors.
Restricted to subscribers or individual electronic text purchasers.
"INTEGRATED CIRCUIT MANUFACTURABILITY provides comprehensive coverage of the process and design variables that determine the ease and feasibility of fabrication (or manufacturability) of contemporary VLSI systems and circuits. This book progresses from semiconductor processing to electrical design to system architecture. The material provides a theoretical background as well as case studies, examining the entire design for the manufacturing path from circuit to silicon. Each chapter includes tutorial and practical applications coverage. INTEGRATED CIRCUIT MANUFACTURABILITY illustrates the implications of manufacturability at every level of abstraction, including the effects of defects on the layout, their mapping to electrical faults, and the corresponding approaches to detect such faults. The reader will be introduced to key practical issues normally applied in industry and usually required by quality, product, and design engineering departments in today's design practices: * Yield management strategies * Effects of spot defects * Inductive fault analysis and testing * Fault-tolerant architectures and MCM testing strategies. This book will serve design and product engineers both from academia and industry. It can also be used as a reference or textbook for introductory graduate-level courses on manufacturing.".
Also available in print.
Mode of access: World Wide Web
Description based on PDF viewed 12/21/2015.
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