000 | 03797nam a22004815i 4500 | ||
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001 | 978-1-4614-7324-4 | ||
003 | DE-He213 | ||
005 | 20200420220225.0 | ||
007 | cr nn 008mamaa | ||
008 | 130805s2014 xxu| s |||| 0|eng d | ||
020 |
_a9781461473244 _9978-1-4614-7324-4 |
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024 | 7 |
_a10.1007/978-1-4614-7324-4 _2doi |
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050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
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072 | 7 |
_aTEC008010 _2bisacsh |
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082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aMehta, Ashok B. _eauthor. |
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245 | 1 | 0 |
_aSystemVerilog Assertions and Functional Coverage _h[electronic resource] : _bGuide to Language, Methodology and Applications / _cby Ashok B. Mehta. |
264 | 1 |
_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2014. |
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300 |
_aXXXIII, 356 p. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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505 | 0 | _aIntroduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions - Basics (sequence, property, assert).- Sampled Value Functions   $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- 'expect' -- 'assume' and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800-2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions - LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options (Reference material). | |
520 | _aThis book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage.  Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'.  Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.  Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby reducing drastically their time to design and debug.   �         Covers both SystemVerilog Assertions and SytemVerilog Functional Coverage language and methodologies; �         Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; �         Explains each concept in an easy to understand, step-by-step fashion and applies it to a real example; �         Includes practical labs that enable readers to put in practice the concepts explained in the book. | ||
650 | 0 | _aEngineering. | |
650 | 0 | _aMicroprocessors. | |
650 | 0 | _aElectronics. | |
650 | 0 | _aMicroelectronics. | |
650 | 0 | _aElectronic circuits. | |
650 | 1 | 4 | _aEngineering. |
650 | 2 | 4 | _aCircuits and Systems. |
650 | 2 | 4 | _aElectronics and Microelectronics, Instrumentation. |
650 | 2 | 4 | _aProcessor Architectures. |
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9781461473237 |
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-1-4614-7324-4 |
912 | _aZDB-2-ENG | ||
942 | _cEBK | ||
999 |
_c52175 _d52175 |