000 03065nam a22004815i 4500
001 978-3-319-02378-6
003 DE-He213
005 20200421111843.0
007 cr nn 008mamaa
008 131115s2014 gw | s |||| 0|eng d
020 _a9783319023786
_9978-3-319-02378-6
024 7 _a10.1007/978-3-319-02378-6
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aNoia, Brandon.
_eauthor.
245 1 0 _aDesign-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
_h[electronic resource] /
_cby Brandon Noia, Krishnendu Chakrabarty.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2014.
300 _aXVIII, 245 p. 133 illus., 115 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- Wafer Stacking and 3D Memory Test -- Built-in Self-Test for TSVs -- Pre-Bond TSV Test Through TSV Probing -- Pre-Bond TSV Test Through TSV Probing -- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths -- Post-Bond Test Wrappers and Emerging Test Standards -- Test-Architecture Optimization and Test Scheduling -- Conclusions.
520 _aThis book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects.  The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain.  Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization.  Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.   • Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs; • Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations; • Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.  .
650 0 _aEngineering.
650 0 _aMicroprocessors.
650 0 _aSemiconductors.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aProcessor Architectures.
650 2 4 _aSemiconductors.
700 1 _aChakrabarty, Krishnendu.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783319023779
856 4 0 _uhttp://dx.doi.org/10.1007/978-3-319-02378-6
912 _aZDB-2-ENG
942 _cEBK
999 _c55686
_d55686