000 | 02921nam a22005175i 4500 | ||
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001 | 978-1-4614-1359-2 | ||
003 | DE-He213 | ||
005 | 20200421112037.0 | ||
007 | cr nn 008mamaa | ||
008 | 120925s2013 xxu| s |||| 0|eng d | ||
020 |
_a9781461413592 _9978-1-4614-1359-2 |
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024 | 7 |
_a10.1007/978-1-4614-1359-2 _2doi |
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050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
|
072 | 7 |
_aTEC008010 _2bisacsh |
|
082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aChen, Mingsong. _eauthor. |
|
245 | 1 | 0 |
_aSystem-Level Validation _h[electronic resource] : _bHigh-Level Modeling and Directed Test Generation Techniques / _cby Mingsong Chen, Xiaoke Qin, Heon-Mo Koo, Prabhat Mishra. |
264 | 1 |
_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2013. |
|
300 |
_aXXII, 250 p. _bonline resource. |
||
336 |
_atext _btxt _2rdacontent |
||
337 |
_acomputer _bc _2rdamedia |
||
338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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505 | 0 | _aIntroduction -- Modeling and Specification of SoC Designs -- Automated Generation of Directed Tests -- Functional Test Compaction.- Property Clustering and Learning Techniques -- Decision Ordering Based Learning Techniques -- Synchronized Generation of Directed Tests -- Learning-Oriented Property Decomposition Approaches -- Directed Test Generation for Multicore Architectures -- Test Generation for Cache Coherence Validation.- Reuse of System-Level Tests for Implementation Validation -- Conclusion. | |
520 | _aThis book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions. The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost. | ||
650 | 0 | _aEngineering. | |
650 | 0 | _aMicroprocessors. | |
650 | 0 | _aElectronics. | |
650 | 0 | _aMicroelectronics. | |
650 | 0 | _aElectronic circuits. | |
650 | 1 | 4 | _aEngineering. |
650 | 2 | 4 | _aCircuits and Systems. |
650 | 2 | 4 | _aElectronics and Microelectronics, Instrumentation. |
650 | 2 | 4 | _aProcessor Architectures. |
700 | 1 |
_aQin, Xiaoke. _eauthor. |
|
700 | 1 |
_aKoo, Heon-Mo. _eauthor. |
|
700 | 1 |
_aMishra, Prabhat. _eauthor. |
|
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9781461413585 |
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-1-4614-1359-2 |
912 | _aZDB-2-ENG | ||
942 | _cEBK | ||
999 |
_c56433 _d56433 |