000 03869nam a22004815i 4500
001 978-1-4614-8310-6
003 DE-He213
005 20200421112038.0
007 cr nn 008mamaa
008 131001s2014 xxu| s |||| 0|eng d
020 _a9781461483106
_9978-1-4614-8310-6
024 7 _a10.1007/978-1-4614-8310-6
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aWong, Cheng-Chi.
_eauthor.
245 1 0 _aTurbo Decoder Architecture for Beyond-4G Applications
_h[electronic resource] /
_cby Cheng-Chi Wong, Hsie-Chia Chang.
264 1 _aNew York, NY :
_bSpringer New York :
_bImprint: Springer,
_c2014.
300 _aVIII, 100 p. 36 illus., 3 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- Conventional Architecture of Turbo Decoder -- Turbo Decoder with Parallel Processing -- Low-Complexity Solution for Highly Parallel Architecture -- High Efficiency Solution for Highly Parallel Architecture.
520 _aThis book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications.  The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time.  Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. Several state-of-the-art techniques that improve complexity and/or throughput are introduced.  The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards and enables designs that reconfigure block size and parallelism.  Case studies include the discussions of both throughput and performance of each mode (block size/parallelism/iteration).  This book not only highlights the critical design issues that restrict the speedup of parallel architecture, but it also provides the solutions to overcome these limitations by modifying slightly the turbo codec of modern standards.     �         Offers readers a complete introduction to practical turbo decoder design; �         Describes different design methodologies and explains the trade-offs between performance improvement and overhead; �         Explains modern techniques for state-of-the-art designs; �         Includes simulation and implementation results with respect to various decoder circuit designs; �         Reveals novel approaches to higher operating efficiency of turbo decoders for beyond 4G applications.
650 0 _aEngineering.
650 0 _aMicroprocessors.
650 0 _aElectrical engineering.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aCommunications Engineering, Networks.
650 2 4 _aProcessor Architectures.
700 1 _aChang, Hsie-Chia.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781461483090
856 4 0 _uhttp://dx.doi.org/10.1007/978-1-4614-8310-6
912 _aZDB-2-ENG
942 _cEBK
999 _c56475
_d56475