000 04186nam a22004815i 4500
001 978-94-91216-92-3
003 DE-He213
005 20200421112040.0
007 cr nn 008mamaa
008 130720s2013 fr | s |||| 0|eng d
020 _a9789491216923
_9978-94-91216-92-3
024 7 _a10.2991/978-94-91216-92-3
_2doi
050 4 _aQA75.5-76.95
050 4 _aTK7885-7895
072 7 _aUK
_2bicssc
072 7 _aCOM067000
_2bisacsh
082 0 4 _a004
_223
100 1 _aBen Abdallah, Abderazek.
_eauthor.
245 1 0 _aMulticore Systems On-Chip: Practical Software/Hardware Design
_h[electronic resource] :
_b2nd Edition /
_cby Abderazek Ben Abdallah.
264 1 _aParis :
_bAtlantis Press :
_bImprint: Atlantis Press,
_c2013.
300 _aXXVI, 273 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aAtlantis Ambient and Pervasive Intelligence,
_x1875-7669 ;
_v7
505 0 _aIntroduction to Multicore Systems On-Chip -- Multicore SoCs Design Methods -- Multicore SoC Organization -- 2D Network-on-Chip -- 3D Network-on-Chip -- Network Interface Architecture and Design for 2D/3D NoCs -- Parallelizing Compiler for Single and Multicore Computing -- Power Optimization Techniques for Multicore SoCs -- Soft-Core Processor for Low-Power Embedded -- Dual-Execution Processor Architecture for Embedded -- Case Study: Deign of Embedded Multicore SoC.
520 _aSystem on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing. The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowing to reduce the voltage on each core. Because dynamic power is proportional to the frequency and to the square of the voltage, we get a big gain, even though we may have more cores running. As more and more cores are integrated into these designs to share the ever increasing processing load, the main challenges lie in efficient memory hierarchy, scalable system interconnect, new programming paradigms, and efficient integration methodology for connecting such heterogeneous cores into a single system capable of leveraging their individual flexibility. Current design methods tend toward mixed HW/SW co-designs targeting multicore systems on-chip for specific applications. To decide on the lowest cost mix of cores, designers must iteratively map the device's functionality to a particular HW/SW partition and target architectures. In addition, to connect the heterogeneous cores, the architecture requires high performance complex communication architectures and efficient communication protocols, such as hierarchical bus, point-to-point connection, or Network-on-Chip. Software development also becomes far more complex due to the difficulties in breaking a single processing task into multiple parts that can be processed separately and then reassembled later. This reflects the fact that certain processor jobs cannot be easily parallelized to run concurrently on multiple processing cores and that load balancing between processing cores - especially heterogeneous cores - is very difficult.
650 0 _aComputer science.
650 0 _aComputer hardware.
650 0 _aMicroprocessors.
650 1 4 _aComputer Science.
650 2 4 _aComputer Hardware.
650 2 4 _aProcessor Architectures.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9789491216916
830 0 _aAtlantis Ambient and Pervasive Intelligence,
_x1875-7669 ;
_v7
856 4 0 _uhttp://dx.doi.org/10.2991/978-94-91216-92-3
912 _aZDB-2-SCS
942 _cEBK
999 _c56603
_d56603