000 03642nam a22005895i 4500
001 978-90-481-9644-9
003 DE-He213
005 20200421112052.0
007 cr nn 008mamaa
008 120921s2013 ne | s |||| 0|eng d
020 _a9789048196449
_9978-90-481-9644-9
024 7 _a10.1007/978-90-481-9644-9
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aKrishnaswamy, Smita.
_eauthor.
245 1 0 _aDesign, Analysis and Test of Logic Circuits Under Uncertainty
_h[electronic resource] /
_cby Smita Krishnaswamy, Igor L. Markov, John P. Hayes.
264 1 _aDordrecht :
_bSpringer Netherlands :
_bImprint: Springer,
_c2013.
300 _aXII, 124 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Electrical Engineering,
_x1876-1100 ;
_v115
505 0 _aIntroduction -- Probabilistic Transfer Matrices -- Computing with Probabilistic Transfer Matrices -- Testing Logic Circuits for Probabilistic Faults -- Signtaure-based Reliability Analysis -- Design for Robustness -- Summary and Extensions.
520 _aIntegrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits.  To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits.  The book describes techniques for:   • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;   • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-level optimizations;   • Logic synthesis for greater resilience against soft errors, which improves reliability using moderate overhead in area and performance;   • Test-generation and test-compaction methods aimed at probabilistic faults in logic circuits that facilitate accurate and efficient post-manufacture measurement of soft-error susceptibility.
650 0 _aEngineering.
650 0 _aComputer hardware.
650 0 _aArithmetic and logic units, Computer.
650 0 _aLogic design.
650 0 _aComputer software
_xReusability.
650 0 _aComputer science
_xMathematics.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aArithmetic and Logic Structures.
650 2 4 _aComputer Hardware.
650 2 4 _aPerformance and Reliability.
650 2 4 _aLogic Design.
650 2 4 _aSymbolic and Algebraic Manipulation.
700 1 _aMarkov, Igor L.
_eauthor.
700 1 _aHayes, John P.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9789048196432
830 0 _aLecture Notes in Electrical Engineering,
_x1876-1100 ;
_v115
856 4 0 _uhttp://dx.doi.org/10.1007/978-90-481-9644-9
912 _aZDB-2-ENG
942 _cEBK
999 _c57266
_d57266