000 03195nam a22004695i 4500
001 978-94-007-2427-3
003 DE-He213
005 20200421112223.0
007 cr nn 008mamaa
008 131001s2014 ne | s |||| 0|eng d
020 _a9789400724273
_9978-94-007-2427-3
024 7 _a10.1007/978-94-007-2427-3
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aNeuberger, Gustavo.
_eauthor.
245 1 0 _aProtecting Chips Against Hold Time Violations Due to Variability
_h[electronic resource] /
_cby Gustavo Neuberger, Gilson Wirth, Ricardo Reis.
264 1 _aDordrecht :
_bSpringer Netherlands :
_bImprint: Springer,
_c2014.
300 _aXI, 107 p. 76 illus., 51 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction, Process Variations and Flip-Flops -- Process Variability -- Flip-Flops and Hold Time Violations -- Circuits Under Test -- Measurement Circuits -- Experimental Results -- Systematic and Random Variablility -- Normality Tests -- Probability of Hold Time Violations -- Protecting Circuits Against Hold Time Violations -- Padding Efficiency Of the Proposed Padding Algorithm -- Final Remarks.
520 _aThis book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The consequences of variability to several aspects of circuit design, such as logic gates, storage elements, clock distribution, and any other that can be affected by process variations are discussed, with a key focus on storage elements.  The authors present a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology. To facilitate an on-wafer test, a measurement circuit with a precision compatible to the speed of the technology is described.  �         Provides a comprehensive review of various reliability mechanisms; �         Describes practical modeling and characterization techniques for reliability �         Includes thorough presentation of robust design techniques for major VLSI design units �         Promotes physical understanding with first-principle simulations.
650 0 _aEngineering.
650 0 _aMicroprocessors.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aProcessor Architectures.
700 1 _aWirth, Gilson.
_eauthor.
700 1 _aReis, Ricardo.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9789400724266
856 4 0 _uhttp://dx.doi.org/10.1007/978-94-007-2427-3
912 _aZDB-2-ENG
942 _cEBK
999 _c57514
_d57514