| 000 | 07833nam a2201141 i 4500 | ||
|---|---|---|---|
| 001 | 5236680 | ||
| 003 | IEEE | ||
| 005 | 20200421114110.0 | ||
| 006 | m o d | ||
| 007 | cr |n||||||||| | ||
| 008 | 071029t20152007njua ob 001 0 eng d | ||
| 020 |
_a9780470113950 _qelectronic |
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| 020 |
_z9780470053676 _qpaper |
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| 020 |
_z0470113952 _qelectronic |
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| 024 | 7 |
_a10.1002/0470113952 _2doi |
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| 035 | _a(CaBNVSL)mat05236680 | ||
| 035 | _a(IDAMS)0b00006481094d75 | ||
| 040 |
_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL |
||
| 050 | 4 |
_aTK5105.35. _bC53 2007eb |
|
| 082 | 0 | 4 | _a621.38216 |
| 100 | 1 |
_aChao, H. Jonathan, _d1955- _eauthor. |
|
| 245 | 1 | 0 |
_aHigh performance switches and routers / _cH. Jonathan Chao and Bin Liu. |
| 264 | 1 |
_aHoboken, New Jersey : _bWiley-Interscience, _cc2007. |
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| 300 |
_a1 PDF (1 online resource (xviii, 613 pages)) : _billustrations. |
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| 336 |
_atext _2rdacontent |
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| 337 |
_aelectronic _2isbdmedia |
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| 338 |
_aonline resource _2rdacarrier |
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| 504 | _aIncludes bibliographical references and index. | ||
| 505 | 0 | _aPREFACE -- ACKNOWLEDGMENTS -- 1 INTRODUCTION -- 1.1 Architecture of the Internet: Present and Future -- 1.2 Router Architectures -- 1.3 Commercial Core Router Examples -- 1.4 Design of Core Routers -- 1.5 IP Network Management -- -- 1.6 Outline of the Book -- 2 IP ADDRESS LOOKUP -- 2.1 Overview -- 2.2 Trie-Based Algorithms -- 2.3 Hardware-Based Schemes -- 2.4 IPv6 Lookup -- 2.5 Comparison -- 3 PACKET CLASSIFICATION -- 3.1 Introduction -- 3.2 Trie-Based Classifications -- 3.3 Geometric Algorithms -- 3.4 Heuristic Algorithms -- 3.5 TCAM-Based Algorithms -- 4 TRAFFIC MANAGEMENT -- 4.1 Quality of Service -- 4.2 Integrated Services -- 4.3 Differentiated Services -- 4.4 Traffic Policing and Shaping -- 4.5 Packet Scheduling -- 4.6 Buffer Management -- 5 BASICS OF PACKET SWITCHING -- 5.1 Fundamental Switching Concept -- 5.2 Switch Fabric Classification -- 5.3 Buffering Strategy in Switching Fabrics -- 5.4 Multiplane Switching and Multistage Switching -- 5.5 Performance of Basic Switches -- 6 SHARED-MEMORY SWITCHES -- 6.1 Linked List Approach -- 6.2 Content Addressable Memory Approach -- 6.3 Space-Time-Space Approach -- 6.4 Scaling the Shared-Memory Switches -- 6.5 Multicast Shared-Memory Switches -- 7 INPUT-BUFFERED SWITCHES -- 7.1 Scheduling in VOQ-Based Switches -- 7.2 Maximum Matching -- 7.3 Maximal Matching -- 7.4 Randomized Matching Algorithms -- 7.5 Frame-based Matching -- 7.6 Stable Matching with Speedup -- 8 BANYAN-BASED SWITCHES -- 8.1 Banyan Networks -- 8.2 Batcher-Sorting Network -- 8.3 Output Contention Resolution Algorithms -- 8.4 The Sunshine Switch -- 8.5 Deflection Routing -- 8.6 Multicast Copy Networks -- 9 KNOCKOUT-BASED SWITCHES -- 9.1 Single-Stage Knockout Switch -- 9.2 Channel Grouping Principle -- 9.3 Two-Stage Multicast Output-Buffered ATM Switch (MOBAS) -- 9.4 Appendix -- 10 THE ABACUS SWITCH -- 10.1 Basic Architecture -- 10.2 Multicast Contention Resolution Algorithm -- 10.3 Implementation of Input Port Controller. | |
| 505 | 8 | _a10.4 Performance -- 10.5 ATM Routing and Concentration (ARC) Chip -- 10.6 Enhanced Abacus Switch -- 10.7 Abacus Switch for Packet Switching -- 11 CROSSPOINT BUFFERED SWITCHES -- 11.1 Combined Input and Crosspoint Buffered Switches -- 11.2 Combined Input and Crosspoint Buffered Switches with VOQ -- 11.3 OCF_OCF: Oldest Cell First Scheduling -- 11.4 LQF_RR: Longest Queue First and Round-Robin Scheduling in CIXB-1 -- 11.5 MCBF: Most Critical Buffer First Scheduling -- 12 CLOS-NETWORK SWITCHES -- 12.1 Routing Property of Clos Network Switches -- 12.2 Looping Algorithm -- 12.3 m-Matching Algorithm -- 12.4 Euler Partition Algorithm -- 12.5 Karol's Algorithm -- 12.6 Frame-Based Matching Algorithm for Clos Network (f-MAC) -- 12.7 Concurrent Matching Algorithm for Clos Network (c-MAC) -- 12.8 Dual-Level Matching Algorithm for Clos Network (d-MAC) -- 12.9 The ATLANTA Switch -- 12.10 Concurrent Round-Robin Dispatching (CRRD) Scheme -- 12.11 The Path Switch -- 13 MULTI-PLANE MULTI-STAGE BUFFERED SWITCH -- 13.1 TrueWay Switch Architecture -- 13.2 Packet Scheduling -- 13.3 Stage-To-Stage Flow Control -- 13.4 Port-To-Port Flow Control -- 13.5 Performance Analysis -- 13.6 Prototype -- 14 LOAD-BALANCED SWITCHES -- 14.1 Birkhoff-Von Neumann Switch -- 14.2 Load-Balanced Birkhoff-von Neumann Switches -- 14.3 Load-Balanced Birkhoff-von Neumann SwitchesWith FIFO Service -- 15 OPTICAL PACKET SWITCHES -- 15.1 Opto-Electronic Packet Switches -- 15.2 Optoelectronic Packet Switch Case Study I -- 15.3 Optoelectronic Packet Switch Case Study II -- 15.4 All Optical Packet Switches -- 15.5 Optical Packet Switch with Shared Fiber Delay Lines Single-stage Case -- 15.6 All Optical Packet Switch with Shared Fiber Delay Lines - Three Stage Case -- 16 HIGH-SPEED ROUTER CHIP SET -- 16.1 Network Processors (NPs) -- 16.2 Co-Processors for Packet Classification -- 16.3 Traffic Management Chips -- 16.4 Switching Fabric Chips -- INDEX. | |
| 506 | 1 | _aRestricted to subscribers or individual electronic text purchasers. | |
| 520 | _aAs Internet traffic grows and demands for quality of service become stringent, researchers and engineers can turn to this go-to guide for tested and proven solutions. This text presents the latest developments in high performance switches and routers, coupled with step-by-step design guidance and more than 550 figures and examples to enable readers to grasp all the theories and algorithms used for design and implementation. | ||
| 530 | _aAlso available in print. | ||
| 538 | _aMode of access: World Wide Web. | ||
| 588 | _aDescription based on PDF viewed 12/19/2015. | ||
| 650 | 0 | _aAsynchronous transfer mode. | |
| 650 | 0 | _aRouters (Computer networks) | |
| 650 | 0 | _aComputer network protocols. | |
| 650 | 0 | _aPacket switching (Data transmission) | |
| 655 | 0 | _aElectronic books. | |
| 695 | _aAdmission control | ||
| 695 | _aBandwidth | ||
| 695 | _aBipartite graph | ||
| 695 | _aBuffer storage | ||
| 695 | _aClassification algorithms | ||
| 695 | _aColor | ||
| 695 | _aComplexity theory | ||
| 695 | _aComputer aided manufacturing | ||
| 695 | _aComputer architecture | ||
| 695 | _aData structures | ||
| 695 | _aDegradation | ||
| 695 | _aDelay | ||
| 695 | _aFabrics | ||
| 695 | _aHardware | ||
| 695 | _aIP networks | ||
| 695 | _aIndexes | ||
| 695 | _aIntegrated circuit interconnections | ||
| 695 | _aInternet | ||
| 695 | _aMatrix decomposition | ||
| 695 | _aMemory management | ||
| 695 | _aMicroprocessors | ||
| 695 | _aMultiplexing | ||
| 695 | _aMultiprocessor interconnection | ||
| 695 | _aMultiprotocol label switching | ||
| 695 | _aOptical buffering | ||
| 695 | _aOptical packet switching | ||
| 695 | _aOptical receivers | ||
| 695 | _aOptical switches | ||
| 695 | _aOptical transmitters | ||
| 695 | _aOrganizations | ||
| 695 | _aPacket switching | ||
| 695 | _aParallel processing | ||
| 695 | _aPartitioning algorithms | ||
| 695 | _aProbability | ||
| 695 | _aProcessor scheduling | ||
| 695 | _aProgram processors | ||
| 695 | _aQuality of service | ||
| 695 | _aRandom access memory | ||
| 695 | _aReal time systems | ||
| 695 | _aRegisters | ||
| 695 | _aRouting | ||
| 695 | _aRouting protocols | ||
| 695 | _aScalability | ||
| 695 | _aSchedules | ||
| 695 | _aScheduling algorithm | ||
| 695 | _aSections | ||
| 695 | _aSoftware algorithms | ||
| 695 | _aSorting | ||
| 695 | _aSwitches | ||
| 695 | _aSwitching circuits | ||
| 695 | _aThroughput | ||
| 695 | _aTime division multiplexing | ||
| 700 | 1 | _aLiu, Bin. | |
| 710 | 2 |
_aIEEE Xplore (Online service), _edistributor. |
|
| 776 | 0 | 8 |
_iPrint version: _z9780470053676 |
| 856 | 4 | 2 |
_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5236680 |
| 942 | _cEBK | ||
| 999 |
_c59319 _d59319 |
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