| 000 | 10078nam a2200937 i 4500 | ||
|---|---|---|---|
| 001 | 6266786 | ||
| 003 | IEEE | ||
| 005 | 20200421114418.0 | ||
| 006 | m o d | ||
| 007 | cr |n||||||||| | ||
| 008 | 151221s2012 nju ob 001 eng d | ||
| 020 |
_a9781118347959 _qebook |
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| 020 | _a9786613704153 | ||
| 020 |
_z9781118162637 _qprint |
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| 020 |
_z9781118347928 _qelectronic |
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| 020 | _z6613704156 | ||
| 020 |
_z1118347927 _qelectronic |
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| 020 |
_z1118347951 _qelectronic |
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| 024 | 7 |
_a10.1002/9781118347959 _2doi |
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| 035 | _a(CaBNVSL)mat06266786 | ||
| 035 | _a(IDAMS)0b000064818b36d0 | ||
| 040 |
_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL |
||
| 050 | 4 |
_aTK7868.T5 _b.X68 2008eb |
|
| 082 | 0 | 4 |
_a621.381/32 _223 |
| 100 | 1 |
_aXiu, Liming, _eauthor. |
|
| 245 | 1 | 0 |
_aNanometer frequency synthesis beyond the phase-locked loop / _cLiming Xiu. |
| 264 | 1 |
_aHoboken [New Jersey] : _bJohn Wiley & Sons, _c2012. |
|
| 264 | 2 |
_a[Piscataqay, New Jersey] : _bIEEE Xplore, _c[2012] |
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| 300 | _a1 PDF (340 pages). | ||
| 336 |
_atext _2rdacontent |
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| 337 |
_aelectronic _2isbdmedia |
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| 338 |
_aonline resource _2rdacarrier |
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| 490 | 1 |
_aIEEE Press Series on Microelectronic Systems ; _vv.25 |
|
| 500 | _aIn Wiley online library | ||
| 505 | 0 | _aPREFACE xi -- 1 CLOCK SIGNAL IN ELECTRONIC SYSTEMS 1 -- 1.1 The Significance of Clock Signal 1 -- 1.2 The Characteristics of Clock Signal 5 -- 1.3 Clock Signal Driving Digital System 18 -- 1.4 Clock Signal Driving Sampling System 24 -- 1.5 Extracting Clock Signal From Data: Clock Data Recovery 30 -- 1.6 Clock Usage in System-on-Chip 32 -- 1.7 Two Fields: Clock Generation and Clock Distribution 33 -- 2 CLOCK GENERATION: EXISTING FREQUENCY SYNTHESIS TECHNIQUES 37 -- 2.1 Direct Analog Frequency Synthesis 38 -- 2.2 Direct Digital Frequency Synthesis 39 -- 2.3 Indirect Method (Phase-Locked Loop Based) 41 -- 2.4 The Shared Goal: All Cycles Have Same Length-in-Time 51 -- 3 TIME-AVERAGE-FREQUENCY 53 -- 3.1 The Scale of Level and the Scale of Time 53 -- 3.2 What Is Frequency? 54 -- 3.3 Reinvestigating the Frequency Concept: the Birth of Time-Average-Frequency 56 -- 3.4 Time-Average-Frequency in Circuit Implementation 59 -- 3.5 Average Frequency, Time-Average-Frequency, and Fundamental Frequency 61 -- 3.6 The Need of a Theory 62 -- 3.7 The Summary: Why Do We Need Time-Average-Frequency? 63 -- 4 FLYING-ADDER DIRECT PERIOD SYNTHESIS ARCHITECTURE 65 -- 4.1 The Working Principle 65 -- 4.2 The Major Challenges in the Flying-Adder Circuit 68 -- 4.3 The Circuit of Proof of Concept 74 -- 4.4 The Working Circuitry 77 -- 4.5 Frequency Transfer Function, Frequency Range, Frequency Resolution, and Frequency Switching Speed 87 -- 4.6 The Technique of Post Divider Fractional Bits Recovery 88 -- 4.7 Flying-Adder PLL: FAPLL 90 -- 4.8 Flying-Adder Fractional Divider 91 -- 4.9 Integer-Flying-Adder Architecture 92 -- 4.10 The Algorithm to Search Optimum Parameters 98 -- 4.11 The Construction of the Accumulator 99 -- 4.12 The Construction of the High Speed Multiplex 104 -- 4.13 Non-2's Power Flying-Adder Circuit 107 -- 4.14 Expanding VCO Frequency Range in Nanometer CMOS Processes 109 -- 4.15 Multiple Flying-Adder Synthesizers 110 -- 4.16 Flying-Adder Implementation Styles 111 -- 4.17 Simulation Approaches 112 -- 4.18 The Impact of Input Mismatch on Output Jitter 113 -- 4.19 Flying-Adder Circuit as Digital Controlled Oscillator 127 -- 4.20 Flying-Adder Terminology 128 -- 4.21 Flying-Adder Synthesizer and Time-Average-Frequency: The Experimental Evidence 129 -- 4.22 Time-Average-Frequency and Setup Constraint: Revisit 154 -- 4.23 Sense the Frequency Difference: The Time-Average-Frequency Way 156 -- 4.24 Flying-Adder and Direct Digital Synthesis (DDS): The Difference 157 -- 4.25 Flying-Adder for Phase (Delay) Synthesis 158 -- 4.26 Flying-Adder for Duty Cycle Control 162 -- 4.27 Flying-Adder Synthesizer in Reducing the Number of PLLs in SoC 163. | |
| 505 | 8 | _a5 DIGITAL-TO-FREQUENCY CONVERTER 167 -- 5.1 Two Ways of Representing Information 167 -- 5.2 The Converters for Transforming Information 168 -- 5.3 The Two Cornerstones of the Digital-to-Frequency Converter 170 -- 5.4 The Theoretical Foundation of Flying-Adder Digital-to-Frequency Converter 172 -- 5.5 Convert the Spurious Energy to Noise Energy 193 -- 5.6 Move Spurs Around 198 -- 5.7 Spread the Energy 201 -- 5.8 Performance Merits 205 -- 6 THE NEW FRONTIER IN ELECTRONIC SYSTEM DESIGN 211 -- 6.1 The Clocking Challenges in Reality 211 -- 6.2 Flying-Adder and Its Three Major Application Areas 216 -- 6.3 Flying-Adder for On-chip Frequency Generation 218 -- 6.4 Flying-Adder as Adaptive Clock Generator 222 -- 6.5 Flying-Adder as On-chip VCXO 230 -- 6.6 Flying-Adder for Frame Rate Synchronization and Display Monitor Accommodation 237 -- 6.7 Flying-Adder for Frequency Synchronization in Digital Communication: A Preview 240 -- 6.8 Flying-Adder for Clock Data Recovery 242 -- 6.9 Flying-Adder DLL for Deskew 255 -- 6.10 Flying-Adder for Digital Frequency-Locked Loop (Flying-Adder DFLL) 256 -- 6.11 Flying-Adder for Digital Phase-Locked Loop (Flying-Adder DPLL) 262 -- 6.12 Flying-Adder Technology for Dynamic Frequency Scaling 262 -- 6.13 Flying-Adder as 1-bit DDFS 264 -- 6.14 Flying-Adder for Spread Spectrum Clocking 265 -- 6.15 Flying-Adder for Driving Sampling System 268 -- 6.16 Flying-Adder for Non-uniform Sampling 271 -- 6.17 Flying-Adder as Digital FSK Modulator 273 -- 6.18 Flying-Adder for PWM/PFW DC-DC Power Conversion 274 -- 6.19 Integrate Clocking Chips into Processing Chips 275 -- 7 LOOKING INTO FUTURE: THE ERA OF "TIME" 279 -- 7.1 The Four Fundamental Technologies in Modern Chip Design 279 -- 7.2 "Time"-Based Analog Processing 281 -- 7.3 "Time" and Frequency: Encoding Messages Through Modulation 283 -- 7.4 Manipulate "Time": The Tools 283 -- 7.5 It Is Time to Use "Time" 284 -- APPENDICES 287 -- Appendix 4.A: The VHDL Code for Flying-Adder Synthesizer 287 -- Appendix 4.B: How Close Can It Reach an Integer? 296 -- Appendix 4.C: The Seed and Set in Integer-Flying-Adder PLL 299 -- Appendix 4.D: The Number of Carries From an XIU-Accumulator 302 -- Appendix 5.A: The Flying-Adder State Machine Model (perl) 303 -- Appendix 5.B: The Flying-Adder Waveform Generator (perl) 307 -- Appendix 5.C: The Flying-Adder Waveform Generator with Triangular Modulation (perl) 310 -- Appendix 5.D: The Flying-Adder Waveform Generator with Random Modulation (perl) 314 -- Appendix 6.A: The FA-DCXO Tangent Line and Linearity Measurement 318. | |
| 505 | 8 | _aINDEX 321. | |
| 506 | 1 | _aRestricted to subscribers or individual electronic text purchasers. | |
| 520 | _aIntroducing a new, pioneering approach to integrated circuit designNanometer Frequency Synthesis Beyond Phase-Locked Loop introduces an innovative new way of looking at frequency that promises to open new frontiers in modern integrated circuit (IC) design. While most books on frequency synthesis deal with the phase-locked loop (PLL), this book focuses on the clock signal. It revisits the concept of frequency, solves longstanding problems in on-chip clock generation, and presents a new time-based information processing approach for future chip design.Beginning with the basics, the book explains how clock signal is used in electronic applications and outlines the shortcomings of conventional frequency synthesis techniques for dealing with clock generation problems. It introduces the breakthrough concept of Time-Average-Frequency, presents the Flying-Adder circuit architecture for the implementation of this approach, and reveals a new circuit device, the Digital-to-Frequency Converter (DFC). Lastly, it builds upon these three key components to explain the use of time rather than level to represent information in signal processing.Provocative, inspiring, and chock-full of ideas for future innovations, the book features:. A new way of thinking about the fundamental concept of clock frequency. A new circuit architecture for frequency synthesis: the Flying-Adder direct period synthesis. A new electronic component: the Digital-to-Frequency Converter. A new information processing approach: time-based vs. level-based. Examples demonstrating the power of this technology to build better, cheaper, and faster systemsWritten with the intent of showing readers how to think outside the box, Nanometer Frequency Synthesis Beyond the Phase-Locked Loop is a must-have resource for IC design engineers and researchers as well as anyone who would like to be at the forefront of modern circuit design. | ||
| 530 | _aAlso available in print. | ||
| 538 | _aMode of access: World Wide Web | ||
| 588 | _aDescription based on PDF viewed 12/21/2015. | ||
| 650 | 0 | _aFrequency synthesizers. | |
| 650 | 0 | _aVery high speed integrated circuits. | |
| 650 | 0 | _aTiming circuits. | |
| 655 | 0 | _aElectronic books. | |
| 695 | _aActuators | ||
| 695 | _aAdders | ||
| 695 | _aClocks | ||
| 695 | _aData mining | ||
| 695 | _aDecoding | ||
| 695 | _aDigital-to-frequency converters | ||
| 695 | _aElectronic circuits | ||
| 695 | _aFrequency control | ||
| 695 | _aFrequency conversion | ||
| 695 | _aFrequency shift keying | ||
| 695 | _aFrequency synthesizers | ||
| 695 | _aHuman factors | ||
| 695 | _aIndexes | ||
| 695 | _aJitter | ||
| 695 | _aLibraries | ||
| 695 | _aNoise measurement | ||
| 695 | _aPeriodic structures | ||
| 695 | _aPhase locked loops | ||
| 695 | _aSchedules | ||
| 695 | _aSemiconductor device measurement | ||
| 695 | _aSwitches | ||
| 695 | _aSynchronization | ||
| 695 | _aSynthesizers | ||
| 695 | _aSystem-on-a-chip | ||
| 695 | _aTime frequency analysis | ||
| 695 | _aTuning | ||
| 695 | _aVery large scale integration | ||
| 695 | _aWatches | ||
| 710 | 2 |
_aIEEE Xplore (Online Service), _edistributor. |
|
| 710 | 2 |
_aJohn Wiley & Sons, _epublisher. |
|
| 776 | 0 | 8 |
_iPrint version: _z9781118162637 |
| 830 | 0 |
_aIEEE Press Series on Microelectronic Systems ; _vv.25 |
|
| 856 | 4 | 2 |
_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6266786 |
| 942 | _cEBK | ||
| 999 |
_c59840 _d59840 |
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