000 04136cam a2200649 i 4500
001 ocn974912967
003 OCoLC
005 20220711203431.0
006 m o d
007 cr |||||||||||
008 170307s2017 si ob 001 0 eng
010 _a 2017011202
040 _aDLC
_beng
_erda
_epn
_cDLC
_dOCLCF
_dN$T
_dDG1
_dIDEBK
_dYDX
_dUIU
_dOCLCO
_dRECBK
_dOCLCQ
_dUAB
_dCNCGM
_dUPM
_dOCLCQ
_dDEBSZ
_dOCLCQ
_dNLE
019 _a994093602
020 _a9781119046011
_q(Adobe PDF)
020 _a1119046017
_q(Adobe PDF)
020 _a9781119046004
_q(ePub)
020 _a1119046009
_q(ePub)
020 _a9781119045991
020 _a1119045991
020 _z9781119045939
_q(cloth)
020 _z1119045932
029 1 _aAU@
_b000059700878
029 1 _aCHBIS
_b011150703
029 1 _aCHNEW
_b000964866
029 1 _aCHVBK
_b495227315
029 1 _aCHVBK
_b508821649
029 1 _aDEBSZ
_b493821120
029 1 _aGBVCP
_b1014965802
035 _a(OCoLC)974912967
_z(OCoLC)994093602
042 _apcc
050 0 0 _aTK7874
072 7 _aTEC
_x009070
_2bisacsh
082 0 0 _a621.3815
_223
049 _aMAIN
100 1 _aLi, Suny,
_d1974-
_eauthor.
_97629
245 1 0 _aSiP-system in package design and simulation :
_bMentor EE Flow Advanced Design Guide /
_cSuny Li.
264 1 _aSingapore ;
_aHoboken, NJ :
_bPublishing House of Electronics Industry/Wiley,
_c2017.
300 _a1 online resource
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
504 _aIncludes bibliographical references and index.
505 0 _aSiP design and simulation platform -- Basic knowledge of package -- SiP production process -- New package technologies -- SiP design and simulation flow -- Central library -- Schematic input -- Multi-board project management and schematic concurrent design -- Layout creation and setting -- Constraint rules management -- Wire bond design -- Cavity and chip stack design -- FlipChip and RDL design -- Route and plane -- Embedded passives design -- RF circuit design -- Layout concurrent design -- 3D real-time DRC -- Design review -- Manufacture data output -- SiP simulation technology.
588 0 _aPrint version record and CIP data provided by publisher.
520 _aAn advanced reference documenting, in detail, every step of a real System-in-Package (SiP) design flow Written by an engineer at the leading edge of SiP design and implementation, this book demonstrates how to design SiPs using Mentor EE Flow. Key topics covered include wire bonding, die stacks, cavity, flip chip and RDL (redistribution layer), Embedded Passive, RF design, concurrent design, Xtreme design, 3D real-time DRC (design rule checking), and SiP manufacture. Extensively illustrated throughout, System in Package Design and Simulation covers an array of issues of vital concern for SiP design and fabrication electronics engineers, as well as SiP users, including: -Cavity and sacked dies design -FlipChip and RDL design -Routing and coppering -3D Real-Time DRC check -SiP simulation technology -Mentor SiP Design and Simulation Platform Designed to function equally well as a reference, tutorial, and self-study, System in Package Design and Simulation is an indispensable working resource for every SiP designer, especially those who use Mentor design tools.
650 0 _aIntegrated circuits
_xDesign and construction.
_97630
650 0 _aMultichip modules (Microelectronics)
_xDesign and construction.
_97631
650 7 _aTECHNOLOGY & ENGINEERING
_xMechanical.
_2bisacsh
_97632
650 7 _aIntegrated circuits
_xDesign and construction.
_2fast
_0(OCoLC)fst00975545
_97630
650 7 _aMultichip modules (Microelectronics)
_xDesign and construction.
_2fast
_0(OCoLC)fst01028809
_97631
655 4 _aElectronic books.
_93294
776 0 8 _iPrint version:
_aLi, Suny, 1974-
_tSiP-system in package design and simulation.
_dSingapore ; Hoboken, NJ : John Wiley & Sons, 2017
_z9781119045939
_w(DLC) 2017007232
856 4 0 _uhttps://doi.org/10.1002/9781119045991
_zWiley Online Library
942 _cEBK
994 _a92
_bDG1
999 _c68919
_d68919