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001 on1265465568
003 OCoLC
005 20220711203716.0
006 m o d
007 cr un|---aucuu
008 210828s2021 nju ob 001 0 eng d
040 _aEBLCP
_beng
_cEBLCP
_dYDX
_dDG1
_dOCLCO
_dIEEEE
_dOCLCF
_dUKAHL
019 _a1265344168
020 _a9781119810483
_q(electronic bk. : oBook)
020 _a1119810485
_q(electronic bk. : oBook)
020 _a9781119810469
020 _a1119810469
020 _a9781119810476
_q(electronic bk.)
020 _a1119810477
_q(electronic bk.)
020 _z1119810450
020 _z9781119810452
024 7 _a10.1002/9781119810483
_2doi
029 1 _aAU@
_b000069952158
035 _a(OCoLC)1265465568
_z(OCoLC)1265344168
037 _a9536220
_bIEEE
050 4 _aQA76.87
082 0 4 _a006.3/2
_223
049 _aMAIN
100 1 _aLiu, Albert (Chun-Chen).
_910163
245 1 0 _aArtificial intelligence hardware design
_h[electronic resource] :
_bchallenges and solutions /
_cAlbert Chun Chen Liu and Oscar Ming Kin Law.
260 _aHoboken :
_bIEEE Press :
_bWiley,
_c2021.
300 _a1 online resource (233 p.)
505 0 _aFront Matter -- Introduction -- Deep Learning -- Parallel Architecture -- Streaming Graph Theory -- Convolution Optimization -- In-Memory Computation -- Near-Memory Architecture -- Network Sparsity -- 3D Neural Processing -- Appendix A: Neural Network Topology -- Index
504 _aIncludes bibliographical references and index.
588 0 _aOnline resource; title from PDF title page (John Wiley, viewed August 30, 2021).
520 _aARTIFICIAL INTELLIGENCE HARDWARE DESIGN Learn foundational and advanced topics in Neural Processing Unit design with real-world examples from leading voices in the field In Artificial Intelligence Hardware Design: Challenges and Solutions , distinguished researchers and authors Drs. Albert Chun Chen Liu and Oscar Ming Kin Law deliver a rigorous and practical treatment of the design applications of specific circuits and systems for accelerating neural network processing. Beginning with a discussion and explanation of neural networks and their developmental history, the book goes on to describe parallel architectures, streaming graphs for massive parallel computation, and convolution optimization. The authors offer readers an illustration of in-memory computation through Georgia Tech's Neurocube and Stanford's Tetris accelerator using the Hybrid Memory Cube, as well as near-memory architecture through the embedded eDRAM of the Institute of Computing Technology, the Chinese Academy of Science, and other institutions. Readers will also find a discussion of 3D neural processing techniques to support multiple layer neural networks, as well as information like: A thorough introduction to neural networks and neural network development history, as well as Convolutional Neural Network (CNN) models Explorations of various parallel architectures, including the Intel CPU, Nvidia GPU, Google TPU, and Microsoft NPU, emphasizing hardware and software integration for performance improvement Discussions of streaming graph for massive parallel computation with the Blaize GSP and Graphcore IPU An examination of how to optimize convolution with UCLA Deep Convolutional Neural Network accelerator filter decomposition Perfect for hardware and software engineers and firmware developers, Artificial Intelligence Hardware Design is an indispensable resource for anyone working with Neural Processing Units in either a hardware or software capacity.
590 _bWiley Frontlist Obook All English 2021
650 0 _aNeural networks (Computer science)
_93414
650 0 _aArtificial intelligence.
_93407
650 0 _aComputer engineering.
_910164
650 7 _aArtificial intelligence.
_2fast
_0(OCoLC)fst00817247
_93407
650 7 _aComputer engineering.
_2fast
_0(OCoLC)fst00872078
_910164
650 7 _aNeural networks (Computer science)
_2fast
_0(OCoLC)fst01036260
_93414
655 4 _aElectronic books.
_93294
700 1 _aLaw, Oscar Ming Kin.
_910165
776 0 8 _iPrint version:
_aLiu, Albert (Chun-Chen)
_tArtificial Intelligence Hardware Design
_dNewark : John Wiley & Sons, Incorporated,c2021
_z9781119810452
856 4 0 _uhttps://doi.org/10.1002/9781119810483
_zWiley Online Library
942 _cEBK
994 _a92
_bDG1
999 _c69620
_d69620