| 000 | 04856nam a2201021 i 4500 | ||
|---|---|---|---|
| 001 | 6712668 | ||
| 003 | IEEE | ||
| 005 | 20220712204819.0 | ||
| 006 | m o d | ||
| 007 | cr |n||||||||| | ||
| 008 | 151228s2013 maua ob 001 eng d | ||
| 010 | _z 2013009431 (print) | ||
| 016 | _z 016536438 (print) | ||
| 020 |
_a9780262319096 _qelectronic |
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| 020 |
_z9780262019668 _qhardcover : alk. paper |
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| 020 |
_z0262019663 _qhardcover : alk. paper |
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| 035 | _a(CaBNVSL)mat06712668 | ||
| 035 | _a(IDAMS)0b00006481ff6e43 | ||
| 040 |
_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL |
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| 050 | 4 |
_aTK7885.7 _b.P443 2013eb |
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| 082 | 0 |
_a621.39/2 _223 |
|
| 100 | 1 |
_aPedroni, Volnei A., _eauthor. _92058 |
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| 245 | 1 | 0 |
_aFinite state machines in hardware : _btheory and design (with VHDL and SystemVerilog) / _cVolnei A. Pedroni. |
| 264 | 1 |
_aCambridge, Massachusetts : _bMIT Press, _c[2013] |
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| 264 | 2 |
_a[Piscataqay, New Jersey] : _bIEEE Xplore, _c[2013] |
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| 300 |
_a1 PDF (x, 337 pages) : _billustrations. |
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| 336 |
_atext _2rdacontent |
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| 337 |
_aelectronic _2isbdmedia |
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| 338 |
_aonline resource _2rdacarrier |
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| 504 | _aIncludes bibliographical references (page [331]). | ||
| 506 | 1 | _aRestricted to subscribers or individual electronic text purchasers. | |
| 520 | _aModern, complex digital systems invariably include hardware-implemented finite state machines. The correct design of such parts is crucial for attaining proper system performance. This book offers detailed, comprehensive coverage of the theory and design for any category of hardware-implemented finite state machines. It describes crucial design problems that lead to incorrect or far from optimal implementation and provides examples of finite state machines developed in both VHDL and SystemVerilog (the successor of Verilog) hardware description languages.Important features include: extensive review of design practices for sequential digital circuits; a new division of all state machines into three hardware-based categories, encompassing all possible situations, with numerous practical examples provided in all three categories; the presentation of complete designs, with detailed VHDL and SystemVerilog codes, comments, and simulation results, all tested in FPGA devices; and exercise examples, all of which can be synthesized, simulated, and physically implemented in FPGA boards. Additional material is available on the book's Website. Designing a state machine in hardware is more complex than designing it in software. Although interest in hardware for finite state machines has grown dramatically in recent years, there is no comprehensive treatment of the subject. This book offers the most detailed coverage of finite state machines available. It will be essential for industrial designers of digital systems and for students of electrical engineering and computer science. | ||
| 530 | _aAlso available in print. | ||
| 538 | _aMode of access: World Wide Web | ||
| 588 | _aDescription based on PDF viewed 12/28/2015. | ||
| 650 | 0 |
_aSystemVerilog (Computer hardware description language) _924214 |
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| 650 | 0 |
_aVHDL (Computer hardware description language) _917292 |
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| 650 | 0 |
_aSequential machine theory _xData processing. _924215 |
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| 650 | 0 |
_aComputer systems _xMathematical models. _924216 |
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| 655 | 0 |
_aElectronic books. _93294 |
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| 695 | _aArrays | ||
| 695 | _aAutomata | ||
| 695 | _aBibliographies | ||
| 695 | _aCalculators | ||
| 695 | _aCircuit synthesis | ||
| 695 | _aClocks | ||
| 695 | _aCombinational circuits | ||
| 695 | _aComputational modeling | ||
| 695 | _aComputer architecture | ||
| 695 | _aDetectors | ||
| 695 | _aEncoding | ||
| 695 | _aEquations | ||
| 695 | _aFeedback loop | ||
| 695 | _aFlip-flops | ||
| 695 | _aGraphics | ||
| 695 | _aHardware | ||
| 695 | _aIntegrated circuit modeling | ||
| 695 | _aLatches | ||
| 695 | _aLibraries | ||
| 695 | _aManuals | ||
| 695 | _aMaterials | ||
| 695 | _aMathematical model | ||
| 695 | _aMicrocontrollers | ||
| 695 | _aMonitoring | ||
| 695 | _aPipelines | ||
| 695 | _aPresses | ||
| 695 | _aPropagation delay | ||
| 695 | _aRadiation detectors | ||
| 695 | _aRandom access memory | ||
| 695 | _aRead only memory | ||
| 695 | _aReceivers | ||
| 695 | _aRegisters | ||
| 695 | _aSections | ||
| 695 | _aSequential circuits | ||
| 695 | _aSimulation | ||
| 695 | _aSoftware | ||
| 695 | _aStandards | ||
| 695 | _aSynchronization | ||
| 695 | _aTable lookup | ||
| 695 | _aTransmitters | ||
| 695 | _aVehicles | ||
| 695 | _aWriting | ||
| 710 | 2 |
_aIEEE Xplore (Online Service), _edistributor. _924217 |
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| 710 | 2 |
_aMIT Press, _epublisher. _924218 |
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| 776 | 0 | 8 |
_iPrint version _z9780262019668 |
| 856 | 4 | 2 |
_3Abstract with links to resource _uhttps://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6712668 |
| 942 | _cEBK | ||
| 999 |
_c73351 _d73351 |
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