| 000 | 03956nam a2200949 i 4500 | ||
|---|---|---|---|
| 001 | 5263943 | ||
| 003 | IEEE | ||
| 005 | 20220712205642.0 | ||
| 006 | m o d | ||
| 007 | cr |n||||||||| | ||
| 008 | 151221s1995 njua ob 001 eng d | ||
| 020 |
_a9780470546376 _qelectronic |
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| 020 |
_z9780780310896 _qprint |
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| 020 |
_z0470546379 _qelectronic |
||
| 024 | 7 |
_a10.1109/9780470546376 _2doi |
|
| 035 | _a(CaBNVSL)mat05263943 | ||
| 035 | _a(IDAMS)0b000064810c3d77 | ||
| 040 |
_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL |
||
| 050 | 4 |
_aTK7874.75 _b.S48 1995eb |
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| 082 | 0 | 4 |
_a621.39/5 _222 |
| 100 | 1 |
_aSherwani, N. A., _q(Naveed A.) _eauthor. _926772 |
|
| 245 | 1 | 0 |
_aRouting in the third dimension : _bfrom VLSI chips to MCMs / _cNaveed A. Sherwani, Siddharth Bhingarde, Anand Panyam. |
| 264 | 1 |
_aPiscataway, New Jersey : _bIEEE Press, _cc1995. |
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| 264 | 2 |
_a[Piscataqay, New Jersey] : _bIEEE Xplore, _c[1995] |
|
| 300 |
_a1 PDF (xviii, 358 pages) : _billustrations. |
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| 336 |
_atext _2rdacontent |
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| 337 |
_aelectronic _2isbdmedia |
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| 338 |
_aonline resource _2rdacarrier |
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| 504 | _aIncludes bibliographical references (p. 335-350) and indexes. | ||
| 505 | 0 | _aPreface. Acknowledgments. Introduction. Graphs and Basic Algorithms. Channel Routing and Terminal Assignment. Routing Models. Basic Problems in Routing. Routing Algorithms for the Two-Layer Process. Routing Algorithms for the Three-Layer Process. Routing Algorithms for the Advanced Three-Layered Process. Routing Algorithms for Advanced VLSI and Thin-Film MCMs. Routing Algorithms for General MCMs. Bibliography. Author Index. Subject Index. | |
| 506 | 1 | _aRestricted to subscribers or individual electronic text purchasers. | |
| 520 | _aThis key text addresses the complex computer chips of tomorrow which will consist of several layers of metal interconnect, making the interconnect within a chip or a multichip module a three dimensional problem. You'll find an insightful approach to the algorithmic, cell design issues in chip and MCM routing with an emphasis on techniques for eliminating routing area. | ||
| 530 | _aAlso available in print. | ||
| 538 | _aMode of access: World Wide Web | ||
| 588 | _aDescription based on PDF viewed 12/21/2015. | ||
| 650 | 0 |
_aIntegrated circuits _xVery large scale integration _xComputer-aided design. _913978 |
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| 650 | 0 |
_aMultichip modules (Microelectronics) _xComputer-aided design. _926773 |
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| 655 | 0 |
_aElectronic books. _93294 |
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| 695 | _aAlgorithm design and analysis | ||
| 695 | _aApproximation algorithms | ||
| 695 | _aApproximation methods | ||
| 695 | _aBibliographies | ||
| 695 | _aBipartite graph | ||
| 695 | _aCMOS integrated circuits | ||
| 695 | _aClassification algorithms | ||
| 695 | _aColor | ||
| 695 | _aCompaction | ||
| 695 | _aComplexity theory | ||
| 695 | _aComputer architecture | ||
| 695 | _aDelay | ||
| 695 | _aEstimation | ||
| 695 | _aFabrication | ||
| 695 | _aHeuristic algorithms | ||
| 695 | _aIndexes | ||
| 695 | _aIntegrated circuit interconnections | ||
| 695 | _aIntegrated circuit modeling | ||
| 695 | _aLayout | ||
| 695 | _aLibraries | ||
| 695 | _aLogic gates | ||
| 695 | _aMathematical model | ||
| 695 | _aMetals | ||
| 695 | _aMicroprocessors | ||
| 695 | _aMinimization | ||
| 695 | _aNickel | ||
| 695 | _aPins | ||
| 695 | _aPolynomials | ||
| 695 | _aRegions | ||
| 695 | _aRouting | ||
| 695 | _aShape | ||
| 695 | _aSubstrates | ||
| 695 | _aTerminology | ||
| 695 | _aTransistors | ||
| 695 | _aVery large scale integration | ||
| 695 | _aWire | ||
| 700 | 1 |
_aBhingarde, Siddharth. _926774 |
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| 700 | 1 |
_aPanyam, Anand. _926775 |
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| 710 | 2 |
_aJohn Wiley & Sons, _epublisher. _96902 |
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| 710 | 2 |
_aIEEE Xplore (Online service), _edistributor. _926776 |
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| 776 | 0 | 8 |
_iPrint version: _z9780780310896 |
| 856 | 4 | 2 |
_3Abstract with links to resource _uhttps://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5263943 |
| 942 | _cEBK | ||
| 999 |
_c73874 _d73874 |
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