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001 978-3-319-95207-9
003 DE-He213
005 20220801214041.0
007 cr nn 008mamaa
008 180810s2019 sz | s |||| 0|eng d
020 _a9783319952079
_9978-3-319-95207-9
024 7 _a10.1007/978-3-319-95207-9
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aPóvoa, Ricardo Filipe Sereno.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_936009
245 1 2 _aA New Family of CMOS Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain
_h[electronic resource] /
_cby Ricardo Filipe Sereno Póvoa, João Carlos da Palma Goes, Nuno Cavaco Gomes Horta.
250 _a1st ed. 2019.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2019.
300 _aXVI, 141 p. 121 illus., 53 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- Background and State-of-the-art -- Proposed Architectures and Practical Realizations -- Optimization Design and Simulation Results -- Integrated Prototypes and Experimental Evaluation -- Conclusions.
520 _aThis book addresses the need for energy-efficient amplifiers, providing gain enhancement strategies, suitable to run in parallel with lower supply voltages, by introducing a new family of single-stage cascode-free amplifiers, with proper design, optimization, fabrication and experimental evaluation. The authors describe several topologies, using the UMC 130 nm CMOS technology node with standard-VT devices, for proof-of-concept, achieving results far beyond what is achievable with a classic single-stage folded-cascode amplifier. Readers will learn about a new family of circuits with a broad range of applications, together with the familiarization with a state-of-the-art electronic design automation methodology used to explore the design space of the proposed circuit family. Introduces a new family of CMOS cascode-free amplifiers with high energy-efficiency and improved gain; Describes innovative circuit topologies: the Voltage-Combiners biased OTA (supplied by a 3.3 V source); the Voltage-Combiners biased OTA with Current Starving, for higher gain and energy-efficiency (supplied by a 3.3 V source); the Folded Voltage-Combiners biased OTA (supplied by sources from 1.2 V to 0.9 V); and a Dynamic Voltage-Combiners biased OTA, for high performance analog-to-digital converters (supplied by a 1.2 V source); Enables readers to reach better results than what is achievable with classic single-stage folded-cascode amplifiers, with state-of-the-art results in the context of dynamically biased amplifiers;.
650 0 _aElectronic circuits.
_919581
650 0 _aSignal processing.
_94052
650 0 _aElectronics.
_93425
650 1 4 _aElectronic Circuits and Systems.
_936010
650 2 4 _aSignal, Speech and Image Processing .
_931566
650 2 4 _aElectronics and Microelectronics, Instrumentation.
_932249
700 1 _aGoes, João Carlos da Palma.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_936011
700 1 _aHorta, Nuno Cavaco Gomes.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_936012
710 2 _aSpringerLink (Online service)
_936013
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783319952062
776 0 8 _iPrinted edition:
_z9783319952086
776 0 8 _iPrinted edition:
_z9783030069926
856 4 0 _uhttps://doi.org/10.1007/978-3-319-95207-9
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c75902
_d75902