| 000 | 04000nam a22005415i 4500 | ||
|---|---|---|---|
| 001 | 978-3-030-54828-5 | ||
| 003 | DE-He213 | ||
| 005 | 20220801215928.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 201014s2021 sz | s |||| 0|eng d | ||
| 020 |
_a9783030548285 _9978-3-030-54828-5 |
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| 024 | 7 |
_a10.1007/978-3-030-54828-5 _2doi |
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| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
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_aTEC008010 _2bisacsh |
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| 072 | 7 |
_aTJFC _2thema |
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| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aHerdt, Vladimir. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _947309 |
|
| 245 | 1 | 0 |
_aEnhanced Virtual Prototyping _h[electronic resource] : _bFeaturing RISC-V Case Studies / _cby Vladimir Herdt, Daniel Große, Rolf Drechsler. |
| 250 | _a1st ed. 2021. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2021. |
|
| 300 |
_aXXI, 247 p. 90 illus., 75 illus. in color. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 505 | 0 | _aIntroduction -- Preliminaries -- An Open-Source RISC-V Evaluation Platform -- Formal Verification of SystemC-based Designs using Symbolic Simulation -- Coverage-guided Testing for Scalable Virtual Prototype Verification -- Verification of Embedded Software Binaries using Virtual Prototypes -- Validation of Firmware-Based Power Management using Virtual Prototypes -- Register-Transfer Level Correspondence Analysis -- Conclusion -- Index. | |
| 520 | _aThis book presents a comprehensive set of techniques that enhance all key aspects of a modern Virtual Prototype (VP)-based design flow. The authors emphasize automated formal verification methods, as well as advanced coverage-guided analysis and testing techniques, tailored for SystemC-based VPs and also the associated Software (SW). Coverage also includes VP modeling techniques that handle functional as well as non-functional aspects and also describes correspondence analyses between the Hardware- and VP-level to utilize information available at different levels of abstraction. All approaches are discussed in detail and are evaluated extensively, using several experiments to demonstrate their effectiveness in enhancing the VP-based design flow. Furthermore, the book puts a particular focus on the modern RISC-V ISA, with several case-studies covering modeling as well as VP and SW verification aspects. Provides a comprehensive set of techniques to enhance all key aspects of a Virtual Prototype (VP)-based design flow Includes automated formal verification methods and advanced coverage-guided testing techniques, tailored for SystemC-based VPs Describes efficient, coverage-guided test generation methods for VP-based functional and non-functional software (SW) analysis and verification Includes correspondence analyses to utilize information between different abstraction levels in the design flow Uses several VP and SW verification case-studies that target the modern RISC-V ISA. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
|
| 650 | 0 |
_aEmbedded computer systems. _97792 |
|
| 650 | 0 |
_aCooperating objects (Computer systems). _96195 |
|
| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _947310 |
| 650 | 2 | 4 |
_aEmbedded Systems. _932486 |
| 650 | 2 | 4 |
_aCyber-Physical Systems. _932475 |
| 700 | 1 |
_aGroße, Daniel. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _947311 |
|
| 700 | 1 |
_aDrechsler, Rolf. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _91810 |
|
| 710 | 2 |
_aSpringerLink (Online service) _947312 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030548278 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030548292 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030548308 |
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-030-54828-5 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 942 | _cEBK | ||
| 999 |
_c78014 _d78014 |
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