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020 _a9783658133238
_9978-3-658-13323-8
024 7 _a10.1007/978-3-658-13323-8
_2doi
050 4 _aTK1-9971
072 7 _aTHR
_2bicssc
072 7 _aTEC007000
_2bisacsh
072 7 _aTHR
_2thema
082 0 4 _a621.3
_223
100 1 _aKumm, Martin.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_951562
245 1 0 _aMultiple Constant Multiplication Optimizations for Field Programmable Gate Arrays
_h[electronic resource] /
_cby Martin Kumm.
250 _a1st ed. 2016.
264 1 _aWiesbaden :
_bSpringer Fachmedien Wiesbaden :
_bImprint: Springer Vieweg,
_c2016.
300 _aXXXIII, 206 p. 47 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aHeuristic and ILP-Based Optimal Solutions for the Pipelined Multiple Constant Multiplication Problem -- Methods to Integrate Embedded Multipliers, LUT-Based Constant Multipliers and Ternary (3-Input) Adders -- An Optimized Multiple Constant Multiplication Architecture Using Floating Point Arithmetic. .
520 _aThis work covers field programmable gate array (FPGA)-specific optimizations of circuits computing the multiplication of a variable by several constants, commonly denoted as multiple constant multiplication (MCM). These optimizations focus on low resource usage but high performance. They comprise the use of fast carry-chains in adder-based constant multiplications including ternary (3-input) adders as well as the integration of look-up table-based constant multipliers and embedded multipliers to get the optimal mapping to modern FPGAs. The proposed methods can be used for the efficient implementation of digital filters, discrete transforms and many other circuits in the domain of digital signal processing, communication and image processing. Contents Heuristic and ILP-Based Optimal Solutions for the Pipelined Multiple Constant Multiplication Problem Methods to Integrate Embedded Multipliers, LUT-Based Constant Multipliers and Ternary (3-Input) Adders An Optimized Multiple Constant Multiplication Architecture Using Floating Point Arithmetic Target Groups Researchers and students of electrical engineering and computer science Practitioners in the area of FPGAs and signal processing or digital arithmetic The Author Martin Kumm is working as a postdoctoral researcher at the University of Kassel. His current research interests are digital arithmetic, digital signal processing and discrete optimization, all in the context of field programmable gate arrays. .
650 0 _aElectrical engineering.
_951563
650 0 _aComputers.
_98172
650 0 _aEngineering mathematics.
_93254
650 0 _aEngineering—Data processing.
_931556
650 1 4 _aElectrical and Electronic Engineering.
_951564
650 2 4 _aComputer Hardware.
_933420
650 2 4 _aMathematical and Computational Engineering Applications.
_931559
710 2 _aSpringerLink (Online service)
_951565
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783658133221
776 0 8 _iPrinted edition:
_z9783658133245
856 4 0 _uhttps://doi.org/10.1007/978-3-658-13323-8
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c78792
_d78792