| 000 | 03281nam a22005055i 4500 | ||
|---|---|---|---|
| 001 | 978-3-319-30607-0 | ||
| 003 | DE-He213 | ||
| 005 | 20220801221858.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 160225s2016 sz | s |||| 0|eng d | ||
| 020 |
_a9783319306070 _9978-3-319-30607-0 |
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| 024 | 7 |
_a10.1007/978-3-319-30607-0 _2doi |
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| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aSayil, Selahattin. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _958505 |
|
| 245 | 1 | 0 |
_aSoft Error Mechanisms, Modeling and Mitigation _h[electronic resource] / _cby Selahattin Sayil. |
| 250 | _a1st ed. 2016. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2016. |
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| 300 |
_aXI, 105 p. 81 illus., 35 illus. in color. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 505 | 0 | _aIntroduction -- Mitigation of Single Event Effects -- Transmission Gate (TG) Based Soft Error Mitigation Methods -- Single Event Soft Error Mechanisms -- Modeling Single Event Crosstalk Noise in Nanometer Technologies -- Modeling of Single Event Coupling Delay and Speedup Effects -- Single Event Upset Hardening of Interconnects -- Soft-Error Aware Power Optimization -- Dynamic Threshold Technique for Soft Error and Soft Delay Mitigation. | |
| 520 | _aThis book introduces readers to various radiation soft-error mechanisms such as soft delays, radiation induced clock jitter and pulses, and single event (SE) coupling induced effects. In addition to discussing various radiation hardening techniques for combinational logic, the author also describes new mitigation strategies targeting commercial designs. Coverage includes novel soft error mitigation techniques such as the Dynamic Threshold Technique and Soft Error Filtering based on Transmission gate with varied gate and body bias. The discussion also includes modeling of SE crosstalk noise, delay and speed-up effects. Various mitigation strategies to eliminate SE coupling effects are also introduced. Coverage also includes the reliability of low power energy-efficient designs and the impact of leakage power consumption optimizations on soft error robustness. The author presents an analysis of various power optimization techniques, enabling readers to make design choices that reduce static power consumption and improve soft error reliability at the same time. . | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
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| 650 | 0 |
_aMicroprocessors. _958506 |
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| 650 | 0 |
_aComputer architecture. _93513 |
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| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _958507 |
| 650 | 2 | 4 |
_aProcessor Architectures. _958508 |
| 710 | 2 |
_aSpringerLink (Online service) _958509 |
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| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319306063 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319306087 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319808482 |
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-319-30607-0 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 942 | _cEBK | ||
| 999 |
_c80154 _d80154 |
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