| 000 | 03673nam a22005535i 4500 | ||
|---|---|---|---|
| 001 | 978-3-319-42037-0 | ||
| 003 | DE-He213 | ||
| 005 | 20220801222524.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 160729s2017 sz | s |||| 0|eng d | ||
| 020 |
_a9783319420370 _9978-3-319-42037-0 |
||
| 024 | 7 |
_a10.1007/978-3-319-42037-0 _2doi |
|
| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
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_aTEC008010 _2bisacsh |
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| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aLourenço, Nuno. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _961935 |
|
| 245 | 1 | 0 |
_aAutomatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects _h[electronic resource] / _cby Nuno Lourenço, Ricardo Martins, Nuno Horta. |
| 250 | _a1st ed. 2017. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2017. |
|
| 300 |
_aXXVII, 182 p. 112 illus., 90 illus. in color. _bonline resource. |
||
| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
||
| 505 | 0 | _aIntroduction -- Previous Works on Automatic Analog IC Sizing -- AIDA-C Architecture -- Multi-Objective Optimization Kernel -- AIDA-C Circuit Sizing Results -- Layout-Aware Circuit Sizing -- AIDA-C Layout-aware Circuit Sizing Results -- Conclusions. | |
| 520 | _aThis book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit’s performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
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| 650 | 0 |
_aMicroprocessors. _961936 |
|
| 650 | 0 |
_aComputer architecture. _93513 |
|
| 650 | 0 |
_aElectronics. _93425 |
|
| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _961937 |
| 650 | 2 | 4 |
_aProcessor Architectures. _961938 |
| 650 | 2 | 4 |
_aElectronics and Microelectronics, Instrumentation. _932249 |
| 700 | 1 |
_aMartins, Ricardo. _eauthor. _0(orcid)0000-0002-8251-1415 _1https://orcid.org/0000-0002-8251-1415 _4aut _4http://id.loc.gov/vocabulary/relators/aut _961939 |
|
| 700 | 1 |
_aHorta, Nuno. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _961940 |
|
| 710 | 2 |
_aSpringerLink (Online service) _961941 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319420363 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319420387 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319824857 |
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-319-42037-0 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 942 | _cEBK | ||
| 999 |
_c80860 _d80860 |
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