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001 978-3-031-01735-3
003 DE-He213
005 20240730163654.0
007 cr nn 008mamaa
008 220601s2012 sz | s |||| 0|eng d
020 _a9783031017353
_9978-3-031-01735-3
024 7 _a10.1007/978-3-031-01735-3
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aMuralimanohar, Naveen.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_979864
245 1 0 _aPhase Change Memory
_h[electronic resource] :
_bFrom Devices to Systems /
_cby Naveen Muralimanohar, Moinuddin K. Qureshi, Sudhanva Gurumurthi, Bipin Rajendran.
250 _a1st ed. 2012.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2012.
300 _aXIV, 122 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSynthesis Lectures on Computer Architecture,
_x1935-3243
505 0 _aNext Generation Memory Technologies -- Architecting PCM for Main Memories -- Tolerating Slow Writes in PCM -- Wear Leveling for Durability -- Wear Leveling Under Adversarial Settings -- Error Resilience in Phase Change Memories -- Storage and System Design With Emerging Non-Volatile Memories.
520 _aAs conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveys the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions to enable PCM for main memories. Finally, the authors explore the impact of such byte-addressable non-volatile memories on future storage and system designs. Table of Contents: Next Generation Memory Technologies / Architecting PCM for Main Memories / Tolerating Slow Writes in PCM / Wear Leveling for Durability / Wear Leveling Under Adversarial Settings / Error Resilience in Phase Change Memories /Storage and System Design With Emerging Non-Volatile Memories.
650 0 _aElectronic circuits.
_919581
650 0 _aMicroprocessors.
_979865
650 0 _aComputer architecture.
_93513
650 1 4 _aElectronic Circuits and Systems.
_979866
650 2 4 _aProcessor Architectures.
_979867
700 1 _aQureshi, Moinuddin K.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_979868
700 1 _aGurumurthi, Sudhanva.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_979869
700 1 _aRajendran, Bipin.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_979870
710 2 _aSpringerLink (Online service)
_979871
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783031006074
776 0 8 _iPrinted edition:
_z9783031028632
830 0 _aSynthesis Lectures on Computer Architecture,
_x1935-3243
_979872
856 4 0 _uhttps://doi.org/10.1007/978-3-031-01735-3
912 _aZDB-2-SXSC
942 _cEBK
999 _c84862
_d84862