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020 _a9783540766506
_9978-3-540-76650-6
024 7 _a10.1007/978-3-540-76650-6
_2doi
050 4 _aQA76.758
072 7 _aUMZ
_2bicssc
072 7 _aCOM051230
_2bisacsh
072 7 _aUMZ
_2thema
082 0 4 _a005.1
_223
245 1 0 _aFormal Methods and Software Engineering
_h[electronic resource] :
_b9th International Conference on Formal Engineering Methods, ICFEM 2007, Boca Raton, Florida, USA, November 14-15, 2007, Proceedings /
_cedited by Michael Butler, Michael G. Hinchey, Maria M. Larrondo-Petrie.
250 _a1st ed. 2007.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2007.
300 _aVIII, 387 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aProgramming and Software Engineering,
_x2945-9168 ;
_v4789
505 0 _aInvited Talks -- A System Development Process with Event-B and the Rodin Platform -- Challenges in Software Certification -- Security and Knowledge -- Integrating Formal Methods with System Management -- Formal Engineering of XACML Access Control Policies in VDM++ -- A Verification Framework for Agent Knowledge -- Embedded Systems -- From Model-Based Design to Formal Verification of Adaptive Embedded Systems -- Machine-Assisted Proof Support for Validation Beyond Simulink -- VeSTA: A Tool to Verify the Correct Integration of a Component in a Composite Timed System -- Testing -- Integrating Specification-Based Review and Testing for Detecting Errors in Programs -- Testing for Refinement in CSP -- Reducing Test Sequence Length Using Invertible Sequences -- Automated Analysis -- Model Checking with SAT-Based Characterization of ACTL Formulas -- Automating Refinement Checking in Probabilistic System Design -- Model Checking in Practice: Analysis of Generic Bootloader Using SPIN -- Model Checking Propositional Projection Temporal Logic Based on SPIN -- Hardware -- A Denotational Semantics for Handel-C Hardware Compilation -- Automatic Generation of Verified Concurrent Hardware -- Modeling and Verification of Master/Slave Clock Synchronization Using Hybrid Automata and Model-Checking -- Concurrency -- Efficient Symbolic Execution of Large Quantifications in a Process Algebra -- Formalizing SANE Virtual Processor in Thread Algebra -- Calculating and Composing Progress Properties in Terms of the Leads-to Relation -- Erratum -- Erratum to: Challenges in Software Certification.
650 0 _aSoftware engineering.
_94138
650 0 _aComputer programming.
_94169
650 0 _aComputer science.
_99832
650 0 _aCompilers (Computer programs).
_93350
650 1 4 _aSoftware Engineering.
_94138
650 2 4 _aProgramming Techniques.
_9129794
650 2 4 _aModels of Computation.
_931806
650 2 4 _aComputer Science Logic and Foundations of Programming.
_942203
650 2 4 _aCompilers and Interpreters.
_931853
700 1 _aButler, Michael.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9129795
700 1 _aHinchey, Michael G.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9129796
700 1 _aLarrondo-Petrie, Maria M.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9129797
710 2 _aSpringerLink (Online service)
_9129798
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783540766483
776 0 8 _iPrinted edition:
_z9783540845782
830 0 _aProgramming and Software Engineering,
_x2945-9168 ;
_v4789
_9129799
856 4 0 _uhttps://doi.org/10.1007/978-3-540-76650-6
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