000 | 06010nam a22006495i 4500 | ||
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001 | 978-3-540-78610-8 | ||
003 | DE-He213 | ||
005 | 20240730184105.0 | ||
007 | cr nn 008mamaa | ||
008 | 100301s2008 gw | s |||| 0|eng d | ||
020 |
_a9783540786108 _9978-3-540-78610-8 |
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024 | 7 |
_a10.1007/978-3-540-78610-8 _2doi |
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_aUYA _2bicssc |
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_a004.0151 _223 |
245 | 1 | 0 |
_aReconfigurable Computing: Architectures, Tools, and Applications _h[electronic resource] : _b4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings / _cedited by Roger Woods, Katherine Compton, Christos Bourganis, Pedro C. Diniz. |
250 | _a1st ed. 2008. | ||
264 | 1 |
_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg : _bImprint: Springer, _c2008. |
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300 |
_aXIV, 346 p. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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490 | 1 |
_aTheoretical Computer Science and General Issues, _x2512-2029 ; _v4943 |
|
505 | 0 | _aKeynotes -- Synthesizing FPGA Circuits from Parallel Programs -- From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing -- The von Neumann Syndrome and the CS Education Dilemma -- Programming and Compilation -- Optimal Unroll Factor for Reconfigurable Architectures -- Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems -- DNA and String Processing Applications -- DNA Physical Mapping on a Reconfigurable Platform -- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension -- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs -- Scientific Applications -- A Custom Processor for a TDMA Solver in a CFD Application -- A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation -- Reconfigurable Computing Hardware and Systems -- Physical Design of FPGA Interconnect to Prevent Information Leakage -- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs -- Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems -- Image Processing -- FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor -- A Parallel Hardware Architecture for Image Feature Detection -- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System -- Run-Time Behavior -- A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems -- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor -- Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens -- Instruction Set Extension -- ARISE Machines: Extending Processors with Hybrid Accelerators -- The Instruction-Set Extension Problem: A Survey -- Random Number Generation and Financial Computation -- An FPGA Run-Time Parameterisable Log-Normal Random Number Generator -- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA -- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models -- Posters -- Hybrid-Mode Floating-Point FPGA CORDIC Co-processor -- Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard -- Creating the World's Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications -- Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs -- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures -- PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications -- Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip -- Efficiency of Dynamic Reconfigurable Datapath Extensions - A Case Study -- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices -- Data Reallocation by Exploiting FPGA Configuration Mechanisms -- A Networked, Lightweight and Partially Reconfigurable Platform -- Neuromolecularware - A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis -- An FPGA Configuration Scheme for Bitstream Protection -- Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. | |
650 | 0 |
_aComputer science. _99832 |
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650 | 0 |
_aComputers. _98172 |
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650 | 0 |
_aMicroprocessors. _9134497 |
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650 | 0 |
_aComputer architecture. _93513 |
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650 | 0 |
_aComputer networks . _931572 |
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650 | 0 |
_aElectronic digital computers _xEvaluation. _921495 |
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650 | 0 |
_aComputer systems. _9134498 |
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650 | 1 | 4 |
_aTheory of Computation. _9134499 |
650 | 2 | 4 |
_aComputer Hardware. _933420 |
650 | 2 | 4 |
_aProcessor Architectures. _9134500 |
650 | 2 | 4 |
_aComputer Communication Networks. _9134501 |
650 | 2 | 4 |
_aSystem Performance and Evaluation. _932047 |
650 | 2 | 4 |
_aComputer System Implementation. _938514 |
700 | 1 |
_aWoods, Roger. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt _9134502 |
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700 | 1 |
_aCompton, Katherine. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt _9134503 |
|
700 | 1 |
_aBourganis, Christos. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt _9134504 |
|
700 | 1 |
_aDiniz, Pedro C. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt _9134505 |
|
710 | 2 |
_aSpringerLink (Online service) _9134506 |
|
773 | 0 | _tSpringer Nature eBook | |
776 | 0 | 8 |
_iPrinted edition: _z9783540786092 |
776 | 0 | 8 |
_iPrinted edition: _z9783540871101 |
830 | 0 |
_aTheoretical Computer Science and General Issues, _x2512-2029 ; _v4943 _9134507 |
|
856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-540-78610-8 |
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