Phase Change Memory (Record no. 84862)

000 -LEADER
fixed length control field 03508nam a22005295i 4500
001 - CONTROL NUMBER
control field 978-3-031-01735-3
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20240730163654.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 220601s2012 sz | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783031017353
-- 978-3-031-01735-3
082 04 - CLASSIFICATION NUMBER
Call Number 621.3815
100 1# - AUTHOR NAME
Author Muralimanohar, Naveen.
245 10 - TITLE STATEMENT
Title Phase Change Memory
Sub Title From Devices to Systems /
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2012.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XIV, 122 p.
490 1# - SERIES STATEMENT
Series statement Synthesis Lectures on Computer Architecture,
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Next Generation Memory Technologies -- Architecting PCM for Main Memories -- Tolerating Slow Writes in PCM -- Wear Leveling for Durability -- Wear Leveling Under Adversarial Settings -- Error Resilience in Phase Change Memories -- Storage and System Design With Emerging Non-Volatile Memories.
520 ## - SUMMARY, ETC.
Summary, etc As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveys the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions to enable PCM for main memories. Finally, the authors explore the impact of such byte-addressable non-volatile memories on future storage and system designs. Table of Contents: Next Generation Memory Technologies / Architecting PCM for Main Memories / Tolerating Slow Writes in PCM / Wear Leveling for Durability / Wear Leveling Under Adversarial Settings / Error Resilience in Phase Change Memories /Storage and System Design With Emerging Non-Volatile Memories.
700 1# - AUTHOR 2
Author 2 Qureshi, Moinuddin K.
700 1# - AUTHOR 2
Author 2 Gurumurthi, Sudhanva.
700 1# - AUTHOR 2
Author 2 Rajendran, Bipin.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier https://doi.org/10.1007/978-3-031-01735-3
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
264 #1 -
-- Cham :
-- Springer International Publishing :
-- Imprint: Springer,
-- 2012.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuits.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Microprocessors.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computer architecture.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Processor Architectures.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
-- 1935-3243
912 ## -
-- ZDB-2-SXSC

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