Phase Change Memory [electronic resource] : From Devices to Systems / by Naveen Muralimanohar, Moinuddin K. Qureshi, Sudhanva Gurumurthi, Bipin Rajendran.
By: Muralimanohar, Naveen [author.].
Contributor(s): Qureshi, Moinuddin K [author.] | Gurumurthi, Sudhanva [author.] | Rajendran, Bipin [author.] | SpringerLink (Online service).
Material type: BookSeries: Synthesis Lectures on Computer Architecture: Publisher: Cham : Springer International Publishing : Imprint: Springer, 2012Edition: 1st ed. 2012.Description: XIV, 122 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783031017353.Subject(s): Electronic circuits | Microprocessors | Computer architecture | Electronic Circuits and Systems | Processor ArchitecturesAdditional physical formats: Printed edition:: No title; Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access onlineNext Generation Memory Technologies -- Architecting PCM for Main Memories -- Tolerating Slow Writes in PCM -- Wear Leveling for Durability -- Wear Leveling Under Adversarial Settings -- Error Resilience in Phase Change Memories -- Storage and System Design With Emerging Non-Volatile Memories.
As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveys the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions to enable PCM for main memories. Finally, the authors explore the impact of such byte-addressable non-volatile memories on future storage and system designs. Table of Contents: Next Generation Memory Technologies / Architecting PCM for Main Memories / Tolerating Slow Writes in PCM / Wear Leveling for Durability / Wear Leveling Under Adversarial Settings / Error Resilience in Phase Change Memories /Storage and System Design With Emerging Non-Volatile Memories.
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